Performance Evaluation of Ring Counter using Gated Clock

  • Authors

    • Pushpa Mala S
    • Bharath S P
    • Anjum .
    • Aniket Kumar
    • Debolina Kundu
    2018-07-20
    https://doi.org/10.14419/ijet.v7i3.12.16458
  • Gated clock, Johnson Counter, Ring counter.

  • Abstract

    Minimizing Power dissipation is one of the major concerns in the VLSI industry.Due the rapid growth in technology, there is a tremendous reduction in the chip size. Minimum power consumption has become a priority.In this paper, we propose a low power design techniquefor Ring counter using gated clock.In this paper, we demonstrate the working of ring counter using gated clock.The results are illustrated in Xilinx. The simulation results and the synthesis outputis shown.

     

     

  • References

    1. [1] VeenaBattula, Vishal Moyal,“Design and Analysis of Johnson Counter Based on DFAL Techniqueâ€, International Journal on Recent and Innovation Trends in Computing and Communication, Vol 5, Issue 1,January 2017.

      [2] Heranmoy Maity, Shashank Kumar Singh, Abhijit Dey, AnuDebnath,“A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesâ€, International Journal for Scientific Research & Development, Vol 2, Issue 8, 2014.

      [3] Ranjana Yadav, Alka Agrawal, “Design and Analysis of Low Power Johnson Counter with Improved Performance using MTCMOS and Clock Gatingâ€, International Journal of Science Technology & Engineering, Vol 2, Issue 12, June 2016.

      [4] Upwinder Kaur, Rajesh Mehra, “Low Power CMOS Counter Using Clock Gated Flip-Flopâ€, International Journal of Engineering and Advanced Technology Vol 2, Issue-4, pp. 796-798, April 2013.

      [5] Sani M. Ismail, Saadmaan Rahman, Neelanjana S. Ferdous, “A Design Scheme of Toggle Operation Based Ring Counter with Efficient Clock Gatingâ€, IEEE International Conference on ComputationalIntelligene, Modelling and Simulation, pp.

      [6] Mohammad Dastjerdi- Mottaghi, Anahita Naghilou, Masoud Daneshtalab, Ali Afzali-Kusha, Zainalabedin Navabi, “Hot Block Ring Counter: A Low Power Synchronous Ring Counter,†in IEEE, pp 58-62, 2006.

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  • How to Cite

    Mala S, P., S P, B., ., A., Kumar, A., & Kundu, D. (2018). Performance Evaluation of Ring Counter using Gated Clock. International Journal of Engineering & Technology, 7(3.12), 701-702. https://doi.org/10.14419/ijet.v7i3.12.16458

    Received date: 2018-07-28

    Accepted date: 2018-07-28

    Published date: 2018-07-20