Design of Reconfigurable Block FIR Filter Architecture and Implementation on Hardware

  • Authors

    • Suji S
    • Radhika P
    2018-07-20
    https://doi.org/10.14419/ijet.v7i3.12.16511
  • Reconfigurable block FIR filter, Register unit, Inner product unit(IPU), Pipelined adder, xilinx vivado 2015.4, Zynq xc7020, Cadence.

  • Abstract

    In this paper, a reconfigurable block FIR filter which supports variable filter length is proposed. This recon-figurable block FIR filter uses block based design. Hence, this is an algorithm free architecture. This proposed filter can be used for 5G air interface.The proposed filter produces more efficient power reduction than that of the other filter.The number of LUTs and registers are also reduced in the reconfigurable block FIR filter. The designed filter has been implemented in the ZYNQ xc7020 hardware device using the vivado 2015.4.The technique used for hardware implementation is the IP creation and debug-ging.The debugging helps in the monitoring and triggering the hardware device.

     

     

  • References

    1. [1] Basant Kumar Mohanty, Senior Member, IEEE, and Pramod Kumar Meher, Senior Member, IEEE High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications IEEE transactions on very large scale integration (vlsi) systems, vol. 24, no. 2, February 2016.

      [2] Pramod Kumar Meher, Senior Member, IEEE, Shrutisagar Chan-drasekaran, Member, IEEE, and Abbes Amira, Senior Member, IEEE. FPGA Realization of FIR Filters by Efficient and Flexible systolization Using Distributed Arithmetic. IEEE transactions on signal processing, VOL. 56, NO. 7, JULY 2008.

      [3] Pramod K. Meher Department of Embedded Systems Institute for Info-comm Research, Singapore,IEEE. Megha Maheshwari School of Com-puter Engineering Nanyang Technological University, IEEE. A High-Speed FIR Adaptive Filter Architecture using a Modified Delayed LMS Algorithm 2011 IEEE.

      [4] Sang Yoon Park, Member, IEEE, and Pramod Kumar Meher, Senior Member, IEEE Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter IEEE transactions on circuits and systemsii: express briefs, VOL. 61, NO. 7, JULY 2014.

      [5] Wonsuk Chung, Student Member, IEEE, Chanhong Kim, Sooyong Choi, Member, IEEE,and Daesik Hong, Senior Member, IEEE Synchronization Sequence Design for FBMC/OQAM Systems IEEE transactions on wireless communications, VOL. 15, NO. 10, OCTOBER 2016

      [6] Kuan-Hung Chen and Tzi-Dar Chiueh, Senior Member, IEEE â€A Low-Power Digit-Based Reconfigurable FIR Filter†IEEE transactions on circuits and systemsII: EXPRESS BRIEFS, VOL. 53, NO. 8, AUGUST 2006

      [7] Jongsun Park, Woopyo Jeong, Hamid Mahmoodi-Meimand, Student Member, IEEE, Yongtao Wang, Hunsoo Choo, and Kaushik Roy, Fellow, IEEE, â€Computation Sharing Programmable FIR Filter for Low-Power and High-Performance Applications†IEEE journal of solid-state circuits, VOL. 39, NO. 2, FEBRUARY 2004.

      [8] Indranil Hatai, Indrajit Chakrabarti, Member, IEEE, and Swapna Banerjee, Senior Member, IEEE An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis IEEE transactions on circuits and systems I: Regular Papers, VOL. 62, NO. 4, APRIL 2015

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  • How to Cite

    S, S., & P, R. (2018). Design of Reconfigurable Block FIR Filter Architecture and Implementation on Hardware. International Journal of Engineering & Technology, 7(3.12), 826-830. https://doi.org/10.14419/ijet.v7i3.12.16511

    Received date: 2018-07-29

    Accepted date: 2018-07-29

    Published date: 2018-07-20