Design of All Digital Phase Locked Loop for Wireless Applications

  • Authors

    • Swetha R
    • J Manjula
    • A Ruhan bevi
    2018-07-20
    https://doi.org/10.14419/ijet.v7i3.12.16513
  • All Digital Phase Locked Loop(ADPLL), Dig-ital Loop Filter, Ring Oscillator, Delay Cells, Programmable divider, Cadence

  • Abstract

    This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW.

     

  • References

    1. [1] Nitesh Tripathi, Design of Power Efficient All Digital Phase Locked Loop, IEEE Wispnet 2016.

      [2] C. Li and A. Liscidini, Class-C PA-VCO cell for FSK and GFSK transmitters, IEEE J. Solid-State Circuits, vol. 51, no. 7, pp. 15371546,Jul. 2016.

      [3] A 2.4-GHz ZigBee Transmitter Using a Function-Reuse Class-F DCO-PA and an ADPLL Achieving 22.6 (14.5) System Efciency at 6-dBm (0-dBm) Pout, IEEE 2017.

      [4] Zhiqiang Huang and Howard C. Luong, Fellow, Design and Analysis of Millimeter-Wave Digitally Controlled Oscillators With C-2C Exponen-tially Scaling Switched-Capacitor Ladder , IEEE 2017.

      [5] Interference-Induced DCO Spur Mitigation for Digital Phase Locked Loop in 65-nm CMOS Cheng-Ru Ho, Mike Shuo-Wei Chen

      [6] Shweta Dabas, A New Design of Digitally Controlled Oscillator for Low Power Applications

      [7] Design of High Frequency D Flip Flop Circuit for Phase Detector Application Suraj Kumar Saw1, Preetisudha Meher2 Swarnendu Kumar Chakraborty3

      [8] A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35- m CMOS Technology.

      [9] T. H. Lee, Chap. 15. Gray and Meyer, 10.4 Clock generation: B. Razavi, Design of Analog CMOS Integrated Circuits, Chap. 15, McGraw-Hill, 2001.

  • Downloads

  • How to Cite

    R, S., Manjula, J., & Ruhan bevi, A. (2018). Design of All Digital Phase Locked Loop for Wireless Applications. International Journal of Engineering & Technology, 7(3.12), 836-840. https://doi.org/10.14419/ijet.v7i3.12.16513

    Received date: 2018-07-29

    Accepted date: 2018-07-29

    Published date: 2018-07-20