Efficient design of chaos based 4 bit true random number generator on FPGA

  • Authors

    • Ramji Gupta Maulana Azad National Institute of Technology
    • Alpana Pandey Maulana Azad National Institute of Technology
    • R. K.Baghel Maulana Azad National Institute of Technology
    2018-08-22
    https://doi.org/10.14419/ijet.v7i3.16586
  • Field Programmable Gate Array (FPGA), Chaotic Oscillator, True Random Number Generator (TRNG).

  • Abstract

    True random number generator is a basic building block of any modern secure communication and cryptography system. FPGA implementation of any system has a flexible architecture and low-cost test cycle. In this paper, we present an FPGA implementation of a high speed true random number generator based on chaos oscillator which gives optimize ratio of bit rate to area. The proposed generator is faster and more compact than the existing chaotic oscillator based TRNGs. The Experimental result shows that the proposed TRNG gives 1439 Mbps with optimizing the use of LUTs and registers. It is verified that the generator passes all the NIST SP 800-22 tests. The proposed TRNG is implemented in two FPGA families Nexus 4 (Artix 7) DDR XC7A100TCSG-1 and Basys 3 XC7A35T1CPG236C (Artix 7) using Xilinx Vivado v.2017.3 design suite.

     

  • References

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  • How to Cite

    Gupta, R., Pandey, A., & K.Baghel, R. (2018). Efficient design of chaos based 4 bit true random number generator on FPGA. International Journal of Engineering & Technology, 7(3), 1783-1785. https://doi.org/10.14419/ijet.v7i3.16586

    Received date: 2018-07-31

    Accepted date: 2018-08-08

    Published date: 2018-08-22