Review a Low Power CMOS Charge Pump using Power Gating Techniques to Reduce Leakage Power

  • Authors

    • Vengadeswari N
    • Priscilla Whitin
    2018-08-04
    https://doi.org/10.14419/ijet.v7i3.1.16790
  • Capacitor, Charge pump, Power Gating Techniques, Power leakage, Threshold, Tanner Tools.

  • Abstract

    In most case, charge pump circuit is designed based on capacitor, where voltage is increased at each stage depending on each stage voltage gain. Major elements are all charge pumps circuits one is Pumping capacitors and diode connected MOS.To increases pumping efficiency is very higher for each stage of charge pump circuits. Pumping efficiency are limiting by two parameters one is parasitic capacitance and threshold voltage. The power dissipated from the circuit can be increased by attain of leakage current .To resist this leakage in the circuits the supply voltage is major concern. To reduce the leakage with the help of power gating technique .Charge pump circuits are to be designed and verified by using tanner t-spice tools.

     

  • References

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  • How to Cite

    N, V., & Whitin, P. (2018). Review a Low Power CMOS Charge Pump using Power Gating Techniques to Reduce Leakage Power. International Journal of Engineering & Technology, 7(3.1), 27-30. https://doi.org/10.14419/ijet.v7i3.1.16790

    Received date: 2018-08-03

    Accepted date: 2018-08-03

    Published date: 2018-08-04