A Brief Review for Semiconductor Memory Testing Based on BIST Techniques

  • Authors

    • Nongthombam Imocha Singh
    • Prashant V. Joshi
    2018-08-04
    https://doi.org/10.14419/ijet.v7i3.1.16807
  • BIST, fault functional modeling, flash memory, RAM, and test algorithm.

  • Abstract

    With rapid growth of semiconductor industry and increase in complexity of semiconductor based memory, necessity of stringent testing methodology has become one of top most criteria for memory evaluation. This paper describes the fundamental concepts and overview of Built-In-Self-Test (BIST). It describes different functional faults modeling of RAM and flash memory. This review mentions about testing approaches for memory and illustrates BIST techniques for finding faults, power dissipation, area overhead and test time during testing, also includes research gap and future scope regarding the testing of memory.

     

     

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  • How to Cite

    Imocha Singh, N., & V. Joshi, P. (2018). A Brief Review for Semiconductor Memory Testing Based on BIST Techniques. International Journal of Engineering & Technology, 7(3.1), 98-100. https://doi.org/10.14419/ijet.v7i3.1.16807

    Received date: 2018-08-04

    Accepted date: 2018-08-04

    Published date: 2018-08-04