A Brief Review for Semiconductor Memory Testing Based on BIST Techniques

  • Authors

    • Nongthombam Imocha Singh
    • Prashant V. Joshi
    2018-08-04
    https://doi.org/10.14419/ijet.v7i3.1.16807
  • BIST, fault functional modeling, flash memory, RAM, and test algorithm.

  • With rapid growth of semiconductor industry and increase in complexity of semiconductor based memory, necessity of stringent testing methodology has become one of top most criteria for memory evaluation. This paper describes the fundamental concepts and overview of Built-In-Self-Test (BIST). It describes different functional faults modeling of RAM and flash memory. This review mentions about testing approaches for memory and illustrates BIST techniques for finding faults, power dissipation, area overhead and test time during testing, also includes research gap and future scope regarding the testing of memory.

     

     

  • References

    1. [1] Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai, “Asymmetry dual-LFSR reseeding for low power BISTâ€, Integration, the VLSI journal, Elsevier, vol. 60, 2018, pp. 272-276.

      [2] The international technology roadmap for semiconductors, 2005 edition (ITRS 2005), Semiconductor Industry Association, 2005. Available from: <http:// public.itrs.net/>.

      [3] Aditya Kumar Singh Pundir and Om Prakash Sharma, “CHECKERMARC: A Modified Novel Memory-Testing Approach for Bit-Oriented SRAMâ€, International Journal of Applied Engineering Research, vol. 12, no. 12, 2017, pp. 3023-3028.

      [4] MichaÅ‚ Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jedrzej Solecki, and Jerzy Tyszer, “Low-Power Programmable PRPG With Test Compression Capabilitiesâ€, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 23, no. 6, Jun. 2015, pp. 1063-1076.

      [5] Feng Liang, Luwen Zhang, Shaochong Lei, Guohe Zhang, Kaile Gao, and Bin Liang, “Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemesâ€, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 21, no.4, April 2013 , pp 614-623.

      [6] Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar, “Hybrid BIST optimization using reseeding and test set compactionâ€, Microprocessors and Microsystems, vol. 32, no. 5-6, 2008, , pp. 254-262.

      [7] V. Agrawal, C. Kime, K. Saluja, A tutorial on built-in self test, in: IEEE Design & Test of Computers, IEEE Computer Soc. Press, Silver Spring, MD, March 1993, pp. 73-80 and June 1993, pp. 69-77.

      [8] S. Aritome, R. Shirota, G. Hemink, T. Endoh, F. Mausouka, “Reliability Issues of Flash Memory Cellsâ€, Proc. of the IEEE, vol. 81, no. 5, May 1993, pp. 776-788.

      [9] P. Pavan, R. Bez, P. Olivo, E. Zanoni, “Flash Memory Cells - An Overviewâ€, Proc. of the IEEE, vol. 85, no. 8, Aug, pp. 1248-1271, 1997.

      [10] A.J. van de Goor, “Testing semiconductor memories: Theory and Practiceâ€, John Wiley & Sons, Chichester England, 1991.

      [11] Martirosyan, S., G. Harutyunyan, S. Shoukourian, and Y. Zorian, “An efficient testing methodology for embedded flash memoriesâ€, In East-West Design & Test Symposium (EWDTS), IEEE, 2017, pp. 1-4.

      [12] J.-C. Yeh, C.-F. Wu, K.-L. Cheng, Y.-F. Chou, C.-T. Huang, C.-W. Wu, “Flash memory built-in self-test using march-like algorithmsâ€, Proc. Int. Workshop on Electronic Design Test and Applications (DELTA), Jan 2002, pp. 137-141.

      [13] Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Devicesâ€, Proc. VLSI Test Symp., 1993, pp. 4-9.

      [14] Balwinder Singh, Sukhleen Bindra Narang, Arun Khosla, “Modeling and Simulation of Efficient March Algorithm for Memory Testingâ€, In International Conference on Contemporary Computing. Springer Berlin Heidelberg, 2010, pp. 96-107.

      [15] Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-ChiehYeh, Chih-Tsun Huang, and Cheng-Wen Wu, Automatic Generation of Memory Built-In Self -Test Cores for System on Chip. IEEE conference 2001; (1) pp. 91-96.

      [16] Viswani D Agarwal and Michael L Bushnell, Essentials of Electronic Testing of Digital, Memory and Mixed Signal VLSI Circuits. 3rd ed. New York: Kluwer Academic Publishers; 2000.

      [17] Author,â€Title of the Paperâ€, Proceedings of the conference name, Vol.X, No.X, (200X), pp:XX-YY, http://dx.doi.org/10.1109/MMM.2013.2248651.

      [18] G. Ramprabu, S. Nagarajan, “Design and Analysis of Novel Modified Cross Layer Controller for WMSNâ€, Indian Journal of Science and Technology, Vol 8(5), March 2015, pp.438-444.

  • Downloads

  • How to Cite

    Imocha Singh, N., & V. Joshi, P. (2018). A Brief Review for Semiconductor Memory Testing Based on BIST Techniques. International Journal of Engineering & Technology, 7(3.1), 98-100. https://doi.org/10.14419/ijet.v7i3.1.16807