Design, Implementation and Analysis of 8T SRAM Cell in Memory Array

  • Authors

    • B Kaleeswari
    • S Kaja Mohideen
    2018-08-04
    https://doi.org/10.14419/ijet.v7i3.1.16808
  • WL, BL, BLB and SRAM

  • Abstract

    In modern VLSI designs, static random access memory plays a vital role because of its high performance and low power consumption qualities. As technology is scale down, the importance of the power analysis and leakage current of memory design is increasing. This paper describes about the 1 KB size memory design using SRAM. The proposed design of 8T SRAM single cell in implemented in array structure of size 32x32.The design structure reduces the power by 75% by reducing the leakage current. The proposed 8T SRAM cell is implemented and analyzed in 90nm technology using Digital schematic and Micro wind software.

     

  • References

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  • How to Cite

    Kaleeswari, B., & Kaja Mohideen, S. (2018). Design, Implementation and Analysis of 8T SRAM Cell in Memory Array. International Journal of Engineering & Technology, 7(3.1), 101-105. https://doi.org/10.14419/ijet.v7i3.1.16808

    Received date: 2018-08-04

    Accepted date: 2018-08-04

    Published date: 2018-08-04