Design and Analysis of Heterojunction Tunneling Transistor (HETT) based Standard 6T SRAM Cell

  • Authors

    • B. V. V. Satyanarayana
    • M. Durga Prakash
    2018-08-24
    https://doi.org/10.14419/ijet.v7i3.29.18450
  • Heterojunction Tunneling Transistor (HETT), 6T SRAM Cell, Band to Band Tunneling, Miller Capacitance, Subthreshold Swing, Low Power.

  • Abstract

    Subthreshold Swing (SS) of MOSFETs, which determines the low voltage operation of portable mobile devices, cannot reduce below 60mV/dec that restricts MOSFETs for ultra-low power applications. This work presents design and implementation of high ON current, improved Miller capacitance and reduced Subthreshold Swing heterojunction tunneling transistors (HETTs) for portable electronic systems. The performance of HETT with MOSFET has been compared. In this work, the overlapping of gate/oxide on to source can increase the band to band tunneling (BTBT) and improves the ON current of the transistor. Miller capacitance effect can be reduced by the use of low band offset materials and low energy states of materials like Ge or SiGe. This, in turn, results in better performance characteristics for the transistor.

    The Proposed design and implementation of HETT include both N-type HETT (NHETT) and P-type HETT (PHETT) fabrications and the performance characteristics analysis of both NHETT and PHETT are provided. The advantages and limitations of both NHETT and PHETT for beyond CMOS technologies, in addition to the basic and structural differences between HETTs and conventional MOSFETs to facilitate the use of HETT in place of MOSFET have been elaborated in detail. The construction process of HETT is not at all completely different which is suitable to MOS Design process and is applicable for portable mobile applications. The power analysis of HETT based standard 6T SRAM cell is provided and the performance is verified with the conventional MOSFET based 6T SRAM cell.

     

     

  • References

    1. [1] T.-J. K. Liu and L. Chang, “Moore’s Law: Beyond Planar Silicon CMOS and Into the Nano Eraâ€. New York, NY, USA: Springer-Verlag, pp. 191–223, Sep. 2008.

      [2] Kutila, Mika, Ari Paasio, and TeijoLehtonen. "Simulations on 130 nm technology 6T SRAM cell for Near-Threshold operation." In Circuits and Systems (ISCAS), 2014 IEEE International Symposium on, pp. 1211-1214. IEEE, June 2014.

      [3] S. Borkar, “Design challenges of technology scaling,†IEEE Micro, vol. 19, no. 4, pp. 23–29, Jul. /Aug. 1999.

      [4] W. Y. Choi, B.-G. Park, J. D. Lee, and T.J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,†IEEE Electron Device Lett., vol. 28, no. 8, pp. 743–745, Aug. 2007.

      [5] Ganapathi, Kartik, and SayeefSalahuddin. "Heterojunction vertical band-to-band tunneling transistors for steep subthreshold swing and high on current."IEEE Electron Device Letters, vol. 32, no. 5 pp. 689-691, May 2011.

      [6] A. C. Seabaugh, and Q. Zhang, “Low voltage tunnel transistor for beyond CMOS logic,†Proceedings ofIEEE, vol. 98, no. 12, pp. 2095-2110, Dec. 2010.

      [7] Nayfeh, O. M., Chleirigh, C. N., Hennessy, J., Gomez, L., Hoyt, J. L., & Antoniadis, D. A., "Design of tunneling field-effect transistors using strained-silicon/strained-germanium type-II staggered heterojunctions." IEEE Electron Device Letter, vol. 29, no. 9, pp.1074-1077, Sep. 2008.

      [8] W. Y. Choi, B.-G. Park and T.-J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,†IEEEElectron Device Lett., vol. 28, no. 8, pp. 743–745, Aug. 2007.

      [9] Lee, Yoonmyung, Daeyeon Kim, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, David Blaauw, and Dennis Sylvester. "Low-power circuit analysis and design based on heterojunction tunneling transistors (HETTs)." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 9, pp. 1632-1643, Sep. 2013.

      [10] P.-F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weiss, D. Schmitt Landsiedel, and W. Hansch, “Complementary tunneling transistor for low power application,†Solid-State Electron., vol. 48, no. 12, pp. 2281–2286, Dec. 2004.

      [11] J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris“Band-to-band tunneling in carbon nanotube field-effect transistors,â€Phys. Rev. Lett., vol. 93, no. 19, pp. 196805-1– 196805-4, Nov. 2004.

      [12] M. Luisier and G. Klimeck, “Performance comparisons of tunneling field-effect transistors made of InSb, carbon, and GaSb-InAs broken gap heterostructures,†in Proc. IEEE IEDM, pp. 913–916, Dec. 2009.

      [13] A. M. Ionescu and H. Riel,“Tunnel field-effect transistors as energy-efficient electronic switches,†Nature, vol. 479, no. 7373, pp. 329–337, Nov. 2011.

      [14] Chander, Sweta, Rajashree Das, and S. Baishya."Improved miller capacitance of new heterostructure silicon-on-insulator tunnel FET."TENCON 2015-2015 IEEE Region 10 Conference. IEEE, pp. 1-4, Nov. 2015.

      [15] B V V Satyanarayana and M Durga Prakash, “Analysis of Heterojunction Tunneling Architectures for Ultra Low Power Applications†PONTE International Journal of Sciences and Research, Vol. 73, No. 10, pp. 96-107, Oct 2017.

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  • How to Cite

    Satyanarayana, B. V. V., & Durga Prakash, M. (2018). Design and Analysis of Heterojunction Tunneling Transistor (HETT) based Standard 6T SRAM Cell. International Journal of Engineering & Technology, 7(3.29), 8-11. https://doi.org/10.14419/ijet.v7i3.29.18450

    Received date: 2018-08-28

    Accepted date: 2018-08-28

    Published date: 2018-08-24