Multi path pipelined architecture with twin parallel processing after second stage for high-speed FFT

  • Authors

    • G Prasanna Kumar
    • Pushpa Kotipalli
    • B T. krishna
    2018-08-24
    https://doi.org/10.14419/ijet.v7i3.29.18457
  • FFT, Twiddle Factor, Pipelined, Radix-2, Radix-22, DIF, Latency.

  • This paper presents review on different pipelined FFT architectures and proposes a new pipelined FFT architecture with twin parallel processing after second stage. The proposed architecture follows a novel data flow path, Twiddle factor generation and multiplication is implemented by multiplier and shift registers. The first two stages are implemented by multipath pipelined form after that it follows twin parallel form. The twin parallel form consists of two pipelined units simultaneously generates FFT output values. This architecture reduces latency in a greater extent with a smaller cost of hardware. The proposed architecture compared with previous architectures. The proposed architecture is implemented for Radix-2 and Radix-22 DIF FFT. The throughput of proposed architecture is four.

     

     

  • References

    1. [1] J. Cooley and J. W. Tukey, “An Algorithm for the Machine Calculation of Complex Fourier Series,†Math. Comput.Vol. 19, Pp. 297–301, Apr. 1965.

      [2] L.R. Rabiner and B. Gold. Theory and Application of Digital Signal Processing. Prentice-Hall, Inc., 1975.

      [3] E.H. Wold and A.M. Despain. Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementation. IEEE Trans. Com- Put. C-33(5):414-426, May 1984.

      [4] A.M. Despain. Fourier Transform Computer Using CORDIC Iterations. IEEE Trans. Comput., C-23(10):993-1001, Oct. 1974.

      [5] G. Bi and E. V. Jones. A Pipelined FFT Processor for Word- Sequential Data. IEEE Trans. Acoust., Speech, Signal Processing, 37(12):1982-1985, Dec. 1989.

      [6] W.C. Yeh and C.-W. Jen, “High-Speed And Low-Power Split-Radix FFT,†IEEE Trans. Signal Process., Vol. 51, No. 3, Pp. 864–874, Mar. 2003.

      [7] Y.-T. Lin, P.-Y. Tsai, And T. D. Chiueh, “Low-Power Variable-Length Fast Fourier Transform Processor,†Computers And Digital Techniques, IEE Proceedings -, Vol. 152, No. 4, Pp. 499–506, 2005.

      [8] L. Yang, K. Zhang, H. Liu, J. Huang, And S. Huang, “An Efï¬cient Locally Pipelined FFT Processor,†IEEE Trans. Circuits Syst. II, Exp. Briefs, Vol. 53, No. 7, Pp. 585–589, Jul. 2006.

      [9] M. Shin and H. Lee, “A High-Speed Four Parallel Radix- FFT/IFFT Processor For UWB Applications,†In Proc. IEEE ISCAS, 2008, Pp. 960–963.

      [10] Y. Voronenko And M. Püschel, “Algebraic Signal Processing Theory: Cooley-Tukey Type Algorithms For Real Dfts,†IEEE Trans. Signal Process., Vol. 57, No. 1, Pp. 205–222, Jan. 2009.

      [11] M. Garrido, K. K. Parhi, and J. Grajal, “A Pipelined FFT Architecture for Real-Valued Signals,†IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 56, No. 12, Pp. 2634–2643, Dec. 2009.

      [12] S. Langemeyer, P. Pirsch, And H. Blume, “A FPGA Architecture For Real-Time Processing Of Variable-Length FFTS,†In 2011 IEEE International Conference On Acoustics, Speech And Signal Processing (ICASSP), 2011, Pp. 1705–1708.

      [13] M. Ayinala, M. Brown, And K. Parhi, “Pipelined Parallel FFT Architectures Via Folding Transformation,†IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 6, Pp. 1068–1081, 2012.

      [14] M. Ayinala and K. K. Parhi, “FFT Architectures for Real-Valued Signals Based On Radix-23 and Radix-24 Algorithms,†IEEE Trans. Circuits Syst. I, Reg. Papers, Doi:10.1109/TCSI.2013.224625.

      [15] Sayed Ahmad Salehi, Rasoul Amirfattahi, and Keshab K. Parhi “Pipelined Architectures for Real-Valued FFT AND Hermitian-Symmetric IFFT with Real Datapaths†IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 60, NO. 8, AUGUST 2013.

      [16] Antony Xavier Glittas, Mathini Sellathurai, And Gopalakrishnan Lakshminarayanan A Normal I/O Order Radix-2 FFT Architecture To Process Twin Data Streams For MIMO IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION(VLSI) SYSTEMS, VOL.26, No.6,June 2016.

  • Downloads

  • How to Cite

    Prasanna Kumar, G., Kotipalli, P., & T. krishna, B. (2018). Multi path pipelined architecture with twin parallel processing after second stage for high-speed FFT. International Journal of Engineering & Technology, 7(3.29), 35-38. https://doi.org/10.14419/ijet.v7i3.29.18457