Low power driver receiver topology with delay optimization for on-chip bus interconnects

  • Authors

    • Sridhar T
    • Dr A. S. R Murty
    2018-08-24
    https://doi.org/10.14419/ijet.v7i3.29.18554
  • Static Power, Dynamic Power, Global Bus Interconnect, Driver-Receiver, Capacitive Driven Bus Interconnect.

  • Abstract

    Demands on reducing the delay and power on integrated circuits is increasing with the development of more and more low power devices. The technology scaling and the device design manage static power dissipation. However, the dynamic power dissipation and the delays associated with the bus interconnects have to be addressed separately. A low swing driver-receiver circuit for driving and receiving the signals on the global bus interconnects is presented. Also the capacitively driven interconnects are used for the signal transmission and a series coupling capacitor is introduced at an optimized location along the bus. A substantial improvement of 55% in the delay performance is obtained with the driver-receiver and capacitively driven interconnect topology combine for the data transmission bus

     

     

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  • How to Cite

    T, S., & A. S. R Murty, D. (2018). Low power driver receiver topology with delay optimization for on-chip bus interconnects. International Journal of Engineering & Technology, 7(3.29), 180-184. https://doi.org/10.14419/ijet.v7i3.29.18554

    Received date: 2018-08-29

    Accepted date: 2018-08-29

    Published date: 2018-08-24