Low power driver receiver topology with delay optimization for on-chip bus interconnects

  • Authors

    • Sridhar T
    • Dr A. S. R Murty
    2018-08-24
    https://doi.org/10.14419/ijet.v7i3.29.18554
  • Static Power, Dynamic Power, Global Bus Interconnect, Driver-Receiver, Capacitive Driven Bus Interconnect.

  • Demands on reducing the delay and power on integrated circuits is increasing with the development of more and more low power devices. The technology scaling and the device design manage static power dissipation. However, the dynamic power dissipation and the delays associated with the bus interconnects have to be addressed separately. A low swing driver-receiver circuit for driving and receiving the signals on the global bus interconnects is presented. Also the capacitively driven interconnects are used for the signal transmission and a series coupling capacitor is introduced at an optimized location along the bus. A substantial improvement of 55% in the delay performance is obtained with the driver-receiver and capacitively driven interconnect topology combine for the data transmission bus

     

     

  • References

    1. [1] International technology roadmap for semiconductors. [Online] 2011. www.itrs.net.

      [2] Rabaey, Jan M and Chandrakasan, Anantha P and Nikolic, Borivoje. Digital integrated circuits. S.lPrentice hall Englewood Cliffs, 2002. Vol. 2.

      [3] Dally, William J and Poulton, John W. Digital systems engineering. S.l.Cambridge University Press, 1998.

      [4] Low-swing on-chip signaling techniques: effectiveness and robustness. Zhang, Hui and George, Varghese and Rabaey, Jan M. s.l. IEEE, 2000, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 8, pp. 264--272.

      [5] A low-swing differential signalling scheme for on-chip global interconnects. Narasimhan, Ashok and Kasotiya, Manish and Sridhar, Ramalingam. s.l. IEEE, 2005. VLSI Design, 2005.18th International Conference on. pp. 634--639.

      [6] High performance level conversion for dual V/sub DD/design. Kulkarni, Sarvesh H and Sylvester, Dennis.2004, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, pp. 926-936.

      [7] A direct bootstrapped CMOSlarge capacitive-load driver circuit. Garcia, Jose C and Montiel-Nelson, Juan A and Sosa, Javier and Navarro, Hector. s.l.IEEE, 2004. Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings. pp. 680--681.

      [8] Efficient drivers, receivers and repeaters for low power CMOS bus architectures. Rjoub, A and Koufopavlou, O. Pafos,Cyprus : IEEE, 1999. Electronics, Circuits and Systems, 1999. Proceedings of ICECS'99. The sixth IEEE International Conference on. pp. 789-794.

      [9] E. D. Kyriakis-Bitzaros, S. Nikolaidis, “Design of Low Power CMOS Drivers Based on Charge Recyclingâ€, in the proc. of IEEE International Symposium on Circuits and Systems, vol. 111, pp. 1924-1927, 1997.

      [10] Current-mode tranceiver for silicon Interposer channel. S.Lee, B. Kim, H.Park and J. Sim, IEEE J. Solid-State Circuits 49 (2014) 2044-2053.

      [11] A 95 fJ/b current-mode transceiver for 10mm on-chip interconnect. S. K. Lee, S. H. Lee, D. Sylvester, D. Blaauw and J. Y. Sim, IEEE Solid-State Circuits Conf. (ISSCC) Digest Technical Papers (IEEE, 2013), pp. 262–263.

      [12] Optimization of driver preemphasis for on-chip interconnects. Y. Bai and S. S. Wong, IEEE Trans. Circuits Syst. I: Regular Pap.56 (2009) 033–2041.

      [13] A 32-Gb/s onchip bus with driver pre-emphasis signaling. L. Zhang, J. M. Wilson, R. Bashirullah, L. Luo, J. Xu and P. D. Franzon, IEEE Trans. VLSI Syst. 17 (2009) 1267–1274.

      [14] High speed and low energy capacitively driven on-chip wires. R. Ho, T. Ono, R. D. Hopkins, A. Chow, J. Schauer, F. Y. Liu and R. Drost, IEEE J. Solid-State Circuits 43 (2008) 52–60.

      [15] Power efficient gigabit communication over capacitively driven RC-Limited on-chip interconnects. E. Mensink, D. Schinkel, E. A. M. Klumperink, E. van Tuijl and B. Nauta, IEEE J. Solid-State Circuits 45 (2010)447–457.

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  • How to Cite

    T, S., & A. S. R Murty, D. (2018). Low power driver receiver topology with delay optimization for on-chip bus interconnects. International Journal of Engineering & Technology, 7(3.29), 180-184. https://doi.org/10.14419/ijet.v7i3.29.18554