synchronization mechanism for multi- core processors

  • Authors

    • Poornima P.R
    • Padmaja Devi Ge
    • Rohan Kubde
    https://doi.org/10.14419/ijet.v7i3.29.19194
  • Multi-Core Processor, Synchronization, Dual-Ported Memory.

  • Abstract

    The latest trend in processor design development to get the higher performance is to integrate multiple cores into a single IC or onto multiple dies but in a single chip package. The architectures of the microcontrollers need to look the strict demand within the embedded word. For essential writing, the concurrent programs the heart of multi-core revolution is shared data synchronization. Ideally, synchronization ought to be able to exploit accessible cores for its excellent performance. In this project, tend to present a design for hardware supported synchronization unit that would be enforced on chip and that should be directly accessible by all the various multiple cores. A hardware module memory access controller is used here. It has additionally seen that dual-ported memory will provide the better performance if the multiple cores use inherent parallelism by locking the shared memory by using the tactic called address sensitive method.

     

  • References

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  • How to Cite

    P.R, P., Devi Ge, P., & Kubde, R. (2018). synchronization mechanism for multi- core processors. International Journal of Engineering & Technology, 7(3.29), 367-369. https://doi.org/10.14419/ijet.v7i3.29.19194

    Received date: 2018-09-07

    Accepted date: 2018-09-07