An unveiling FPGA based coding technique to detect and correct the faults by matrix algorithm

  • Abstract
  • Keywords
  • References
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  • Abstract

    In this paper a new approach is implemented to increase the reliability of the memory by detecting and correcting the faults. In present technology the memory circuits are made up of low power technique. When high radiation falls on that circuit, Multiple Cell upsets (MCU) are generated due to this MCU the data will be corrupted. To trounce this, numerous error correction techniques are designed but the main issue is redundancy bits. The proposed technique describes about the reduction of redundancy bits. The information is arranged in the form of matrix (No of rows and no of columns) by adding certain number of rows and performing xor operation with certain no of column we can achieves less redundancy bits. The proposed work is coded using Verilog HDL, simulated using Isim and synthesized using Xilinx 14.2 ISE. The work is implemented on FPGA. No of slices used are 256 compared to previous work 300 and delay is reduced from 7.48ns to 7.2ns. Hence 14% improvement in area and 8.1% improvement in speed is observed.


  • Keywords

    Matrix Code; Error Correction Code (ECC); Multiple Cells Upset (MCUs).

  • References

      [1] Radaelli, Daniele, et al. "Investigation of multi-bit upsets in a 150 nm technology SRAM device." IEEE Transactions on Nuclear Science 52.6 (2005): 2433-2437.

      [2] Ibe, E., Taniguchi, H., Yahagi, Y., Shimbo, K. I., & Toba, T. (2010). Impact of scaling on neutron-induced soft error in SRAMs from a 250 nm to a 22 nm design rule. IEEE Transactions on Electron Devices, 57(7), 1527-1538.

      [3] Olarig, Sompong Paul, and William L. Walker. "Error correction codes." U.S. Patent No. 5,841,795. 24 Nov. 1998.

      [4] Wei, Victor K., and Kyeongcheol Yang. "On the generalized Hamming weights of product codes." IEEE transactions on information theory 39.5 (1993): 1709-1713.

      [5] C. Argyrides and D. K. Pradhan, “Improved decoding algorithm for high reliable reed muller coding,” in Proc. IEEE Int. Syst. On Chip Conf., Sep. 2007, pp. 95–98.

      [6] A. Sanchez-Macian, P. Reviriego, and J. A. Maestro, “Hamming SEC-DAED and extended hamming SEC-DED-TAED codes through selective shortening and bit placement,” IEEE Trans. Device Mater. Rel.,to be published.

      [7] P. Reviriego, M. Flanagan, and J. A. Maestro, “A (64, 45) triple error correction code for memory applications,” IEEE Trans. Device Mater. Rel., vol. 12, no. 1, pp. 101–106, Mar. 2012Wei, Victor K., and Kyeongcheol Yang. "On the generalized Hamming weights of product codes." IEEE transactions on information theory 39.5 (1993): 1709-1713.

      [8] Gill, Balkaran, et al. "An efficient BICS design for SEUs detection and correction in semiconductor memories." Design, Automation and Test in Europe, 2005. Proceedings. IEEE, 2005.

      [9] J. Guo, L. Xiao, Z. Mao and Q. Zhao, "Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22,no. 1, pp. 127-135, Jan. 2014.




Article ID: 19204
DOI: 10.14419/ijet.v7i3.29.19204

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