An unveiling FPGA based coding technique to detect and correct the faults by matrix algorithm

 
 
 
  • Abstract
  • Keywords
  • References
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  • Abstract


    In this paper a new approach is implemented to increase the reliability of the memory by detecting and correcting the faults. In present technology the memory circuits are made up of low power technique. When high radiation falls on that circuit, Multiple Cell upsets (MCU) are generated due to this MCU the data will be corrupted. To trounce this, numerous error correction techniques are designed but the main issue is redundancy bits. The proposed technique describes about the reduction of redundancy bits. The information is arranged in the form of matrix (No of rows and no of columns) by adding certain number of rows and performing xor operation with certain no of column we can achieves less redundancy bits. The proposed work is coded using Verilog HDL, simulated using Isim and synthesized using Xilinx 14.2 ISE. The work is implemented on FPGA. No of slices used are 256 compared to previous work 300 and delay is reduced from 7.48ns to 7.2ns. Hence 14% improvement in area and 8.1% improvement in speed is observed.

     


  • Keywords


    Matrix Code; Error Correction Code (ECC); Multiple Cells Upset (MCUs).

  • References


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Article ID: 19204
 
DOI: 10.14419/ijet.v7i3.29.19204




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