Power analysis of single precision floating point multiplication using Vedic with proposed techniques

  • Authors

    • K V. Gowreesrinivas
    • P Samundiswary
    https://doi.org/10.14419/ijet.v7i3.29.19286
  • Vedic, Compressor, Multiplexer, Verilog.

  • In design of arithmetic circuits low power consumption is one of the basic requirements in recent years. The speed of the device depends on the supply voltage degradation. In this work, a floating-point multiplication for single precision numbers using vedic with different existing techniques like full adder, 4x1 multiplexer, 3:2 compressors and proposed techniques such as modified 2x1 multiplexer moel1 and model2, modified 4:2 compressor logics XOR-MUX and XNOR-XOR-MUX logics are analyzed. The main block involved in the implementation of floating-point multiplication is 24-bit mantissa multiplier block. Further, the optimized techniques are introduced multiplier block to reduce the power dissipation. The proposed techniques such as 2x1 multiplexers, 3:2 compressor with XOR-MUX and XNOR-XOR-MUX logics and 4:2 compressor with XOR-MUX and XNOR-XOR-MUX logics for single precision floating-point multiplication provides better solution in terms of power related issues. The power analysis of single precision floating point multiplication is done and compared with the existing and modified. in terms of Power. Further, the performance metrics of vedic multiplier are analyzed for both existing and proposed techniques are compared. These floating point modules are programmed using Verilog and synthesized using Xilinx Vivado Simulator. From the simulation results, it is concluded that 4:2 compressor with XNOR-XOR-Mux logic achieves better response in terms of power.

     

     

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    V. Gowreesrinivas, K., & Samundiswary, P. (2018). Power analysis of single precision floating point multiplication using Vedic with proposed techniques. International Journal of Engineering & Technology, 7(3.29), 443-446. https://doi.org/10.14419/ijet.v7i3.29.19286