Low Power Clock Gated Delay Buffers

Abstract

Power efficiency is the most important factor in todays electronics. The other factors that are also considered to determine the standard of electronic products are area and speed. Industries are competing to develop products of lesser power consumption, smaller size and faster speed. Though, clubbing all the three factors has not been possible till date, researchers are trying to infuse any of the two factors in todays electronic products. Thus, the idea of reducing power consumption and area in an SRAM based Delay Buffer came up. Portable devices have the requirement of delay buffer when transmitter and receiver work in different frequencies. Existing Delay Buffers use quad gated clock tree ring counter with three levels of gating of the master clock. A SRAM Delay Buffer has been designed with octa and octaX2 gated clock and a clock synchronizer called ADPLL. Clock gating is a  technique which limits the clock for idle Memory units. Findings: The Delay buffers were normally designed with quad gated clock tree distribution. The proposed work shows that the octa and octaX2 gated Delay buffers added with ADPLL adjust the frequency dynamically in run time between transmitter and receiver to achieve low power. The simulation result shows great improvement in power consumption. A 64 x 8 buffer is designed with both octa and octaX2 clock gating, and then the simulation result is compared with quad gated existing delay buffer. The simulation is done using Modelsim 6.6d and power analysis is done both in Altera Quartus and Cadence. Application: Wherever the minimum power is required the follwing buffers are used in any SOC(system-on-chip) application.