Estimation of Power for Reversible Subtractors

  • Authors

    • E. V.Naga Lakshmi
    • Dr. N.Siva Sankara Reddy
    2018-09-22
    https://doi.org/10.14419/ijet.v7i4.5.20021
  • Reversible Logic Circuits (RLC), Reversible Logic Gates (RLG), Power Dissipation, Full Subtracto

  • Abstract

    In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG).   Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor.  Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.

     

     

  • References

    1. [1] EV Naga Lakshmi and Dr.NSS Reddy, “A New Design Of Reversible Full Subtractor†, International Journal of Multidisciplinary Educational Research ISSN: 2277-7881; Impact Factor – 3.318; IF Value:5.16; ISI Value:2.286 Volume 5, Issue 4(5), April 2016

      [2] EV Naga Lakshmi and Dr.NSS Reddy,â€Design of Reversible Full Subtractor Using New Reversible EVNL gate for Low Power Applicationâ€, IEEE International Conference on Inventive Computation Technology , 978-1-5090-1284-8 Volume 3, August 2016.

      [3] M.Perkowski, N.Alhagi, “ Synthesis of small Reversible and Pseudo-Reversible Circuits using Y-Gates and Inverse Y-Gatesâ€, ISMVL 2010.

      [4] H. Thapliyal, M.B Srinivas and H.R Arabnia, “Reversible Logic Synthesis of Half, Full and Parallel Subtractorsâ€, Proc. of the 2005 Intl. Conf. on Embedded Systems and Applications, June 2005, Las Vegas, pp.165-181

      [5] Himanshu Thaplial ,N.Ranganathan “Design of Efficient Reversible Binary Subtractors Based on A New Reversible Gateâ€,2009 IEEE computer society Annual symposium on VLSI.

      [6] E. Fredkin, T Toffoli, “Conservative Logicâ€, Int. J.Theor. Phys, vol. 21, no. 3–4, pp. 219–253, 1982.

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  • How to Cite

    V.Naga Lakshmi, E., & N.Siva Sankara Reddy, D. (2018). Estimation of Power for Reversible Subtractors. International Journal of Engineering & Technology, 7(4.5), 102-104. https://doi.org/10.14419/ijet.v7i4.5.20021

    Received date: 2018-09-22

    Accepted date: 2018-09-22

    Published date: 2018-09-22