Design of a high-performance multiplier based on multiplexer

  • Authors

    • Salah Alkurwy Department of Electronic, College of Engineering, University of Diyala
    2018-12-17
    https://doi.org/10.14419/ijet.v7i4.20999
  • HDL, FPGA, Multiplexer, Multiplier.

  • Abstract

    This paper presents a high-performance multiplier based on 4×1 multiplexer. The 4×1 multiplexer is defined as a combinational logic circuit. It is used to select one of four digital inputs (X) to introduce single output. Two-digit bits of the second group (Y) are used to control the multiplexer. This feature is used to design the proposed 8 - and 12- multipliers. The proposed multipliers are coded using the Verilog hardware description language (HDL). The coded 8×8-bit and 12×12-bit circuits were synthesized, simulated and verified using Quartus II and Modelsim 6.5 software systems. The designed multipliers are compared with the conventional multipliers based on frequency operation speed and the combinational adaptive look-up-tables (ALUTs). The comparison results show the proposed design circuits demonstrate the conventional multipliers in terms of operation-speed by 22.7% and 47%. They, also, reduced the combinational ALUTs by 50% and 52% for both multipliers.

     

     

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  • How to Cite

    Alkurwy, S. (2018). Design of a high-performance multiplier based on multiplexer. International Journal of Engineering & Technology, 7(4), 4182-4185. https://doi.org/10.14419/ijet.v7i4.20999