Low Power Bus Encoding Schemes to Minimization of Crosstalk in Vlsi Interconnects

  • Authors

    • N. Chintaiah
    • G. Umamaheswara Reddy
    https://doi.org/10.14419/ijet.v7i3.29.21396
  • .

  • Abstract

    Data integrity is becoming more challenging task as the technology changes scales down in the direction of Deep Sub Micron (DSM) technology. Interconnects architecture design are now measured the bottleneck in the design of Integrated Circuits. In the DSM technology, a coupling capacitance between interconnects is the foremost factor in the total wire capacitance. The combination effect (capacitance formation) dominates the utilization of energy in the run-instant on chip bus. Bus Encoding is the most commonly used technique to change the data pattern before sending data on the bus it reduces the coupling effect on the bus then cuts the power dissipation. The proposed encoding method is the condition based temporal transition data encoding technique, i.e., upper bit inversion, lower bit inversion, upper-lower bit inversion. By using this encoding techniques, it saves the power and reduces the delay.

  • References

    1. [1] www.semoconductors.org

      [2] Kim. K. W, Beck .K. H, Shanbhag. N, Liu .C. L, and Kang .S. M, “Coupling-driven signal encoding scheme for low power interface design,†in IEEE/ACM International Conference on Computer-aided Design, 2000, pp. 318–321.

      [3] Sideep Paricha-Nikil Dutt "on-chip communication architectures system on chip interconnect" 2008, Elsevier.

      [4] Chintaiah N, Umamaheswarareddy G "Classification and evaluation of the transition reduction data encoding techniques for Low power SOC/NOC Interconnects" i-manager's journal of embedded systems, vol. 6, no.1, pp.35-46. december 2017.

      [5] Stan .M.R, and Burleson .W.P, “Bus invert coding for low power I/O,†IEEE Transactions on Very Large Scale Integration Systems, vol. 3, pp. 49–58, Mar. 1995

      [6] Sumant Ramprasad Naresh R Shanbhag, Ibrahim "A Coding framework for low-power address and data busses," IEEE Transactions on Very Large Scale Integration Systems, vol. 7, pp. 212–221, June. 1999.

      [7] Stan .M.R, and Burleson .W. P, “Limited-weight codes for low-power I/O,†in Proceedings of International Workshop on Low Power Design, Napa, CA, April. 1994, pp. 209–214.

      [8] Subrahmanya.P, Manimegalai .R and Kamakoti. V, “ A bus encoding technique for power and crosstalk minimization, †in Proceedings of International Conference on VLSI Design (VLSID) ,2004, pp. 443–448.

      [9] S. Komatsu, M. Ikeda and K. Asada, “Low power chip interface based on bus data encoding with adaptive code-book method,†Ninth Great Lakes Symposium on VLSI(GLS-VLSI), 1999 , pp. 368 – 371.

      [10] T. Lv, W. Wolf, J. Henkel and H. Lekatsas, “An adaptive dictionary encoding scheme for SOC data buses,†in Proceedings of the Conference on Design, Automation and Test in Europe (DATE), 2002.

      [11] chunjie duan, victor H.cordero calle,sunil p.khatri "Efficient On-chip crosstalk Avoidance CODEC Design,"IEEE Transactions on Very Large Scale Integration Systems, vol. 17, No .4, April. 2009.

      [12] Zahra shirmohammadi, seyed grassem miramadi "On designing an efficient numerical-based forbidden pattern free crosstalk avoidance codec for reliable data transfer of NOCs" Microelectronics reliability,vol.03,pp.304-313,june 2016.

      [13] Y. Zhang, J. Lach, K. Skadron and M. R. Stan, “Odd/even bus invert with two-phase transfer for buses with coupling,†in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pp. 80–83, 2002.

  • Downloads

  • How to Cite

    Chintaiah, N., & Umamaheswara Reddy, G. (2018). Low Power Bus Encoding Schemes to Minimization of Crosstalk in Vlsi Interconnects. International Journal of Engineering & Technology, 7(3.29), 644-647. https://doi.org/10.14419/ijet.v7i3.29.21396

    Received date: 2018-10-09

    Accepted date: 2018-10-09