A novel hybrid error detection and correction method using VHDL

  • Authors

    • Adham Hadi Saleh
    • Omar A. Imran
    • Weaam Talaat Ali
    • Adnan M. Taha
    • Wisam Najm Al-Din Abed
    https://doi.org/10.14419/ijet.v7i4.21538

  • Abstract

    In this paper, we proposed a novel hybrid technique to Error Detection and Correction (EDAC) which is based on merging of two types of linear block codes: Hamming code and CRC (Cyclic Redundancy Check) at the same system. This technique is corrected all types of error by retransmitted or by Forward error correction (FEC). This technique is simply and achieves higher reliability, accuracy and security as compared with other similar methods. The system algorithms is designed and simulation using VHDL ((VHSIC (Very High Speed Inte-grated Circuit Hardware Description Language) to be implemented on FPGA kit (Field Programmable Gate Arrays) with Xilinx ISE 10.1 software program. The proposed system circuits have been designed, implemented, and corrects any types of error successfully.

  • References

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  • How to Cite

    Saleh, A. H., Imran, O. A., Ali, W. T., Taha, A. M., & Al-Din Abed, W. N. (2018). A novel hybrid error detection and correction method using VHDL. International Journal of Engineering & Technology, 7(4), 3048-3053. https://doi.org/10.14419/ijet.v7i4.21538

    Received date: 2018-11-25

    Accepted date: 2018-11-25