FPGA based Implementation and Verification of H.264/AVC Encoder

  • Authors

    • D. Raja Ramesh
    • P. H.S.T.Murthy
    • Maheshwarappa B
    2018-11-26
    https://doi.org/10.14419/ijet.v7i4.29.21649
  • FPGA Prototyping, Architecture, H.264/AVC, motion estimation, HDTV.

  • FPGA prototyping in video processing is extremely essential as it verifies the functionality of the design. The Proposed architecture of H.264/AVC advanced video coding encoder for motion estimation is simulated, synthesized with the vivado Xilinx nexys4 DDR XC7A100TCSG324-2 field programmable gate array device hardware platform. The implemented architecture also compares with the Xilinx zynq-7000 system-on-chip (SOC) with clock frequency of 100MHz on a vivado Xilinx Artix-7 FPGA based with DDR3 memory which is compatible for real time applications for HDTV. This is suitable for high definition television applications, providing up to 60 frames 720p with PSNR around 34 db. 

     

     

  • References

    1. [1] Wang, Y., Wang, Y.: China’s IC Industry Development - from the country of consumption to the power industry, p. 241. Science Press, Beijing (2008)

      [2] Huang, W., Wang, X., et al.: Implementation of high-speed verification platform based on emulator for reDSP & reMAP. In: IEEE 8th International Conference on AISC, pp. 682– 685 (2009)

      [3] Wiegand, T., Sullivan, G.J., et al.: Overview of the H264/AVC Video Coding Standard. IEEE Trans. Circuits Syst. Video Technol. 13(7), 560–576 (2003)

      [4] Puri, A., Chen, X., et al.: Video Coding Using the H.264/MPEG-4 AVC Compression Standard. Signal Processing: Image Communication 19, 793–849 (2004)

      [5] Xilinx Artix-7 FPGA Memory Interface Solutions User GuideV3.91,http://www.xilinx.com/support/documentation/ip_documentation/ mig/v3_91/ug406.pdf

      [6] Babionitakis, K., Lentaris, G., et al.: An Efficient H.264 VLSI Advanced Video Encoder. In: 13th IEEE International Conference on Electronics, Circuits and Systems, pp. 545–548 (2006)

      [7] Chen, T.C., Chien, S.Y., et al.: Analysis and architecture design of an HDTV720p 30frames/s H. 264/AVC encoder. IEEE Trans. Circuits Syst. Video Technol. 16(6), 673– 688 (2006)

      [8] Wang, Y., Wang, Y.: China’s IC Industry Development - from the country of consumption to the power industry,p.241.Science Press, Beijing (2008)

      [9] Huang, W., Wang, X., et al.: Implementation of high-speed verification platform based on emulator for reDSP & reMAP. In: IEEE 8th International Conference on AISC, pp. 682– 685 (2009)

      [10] Wiegand, T., Sullivan, G.J., et al.: Overview of the H264/AVC Video Coding Standard. IEEE Trans. Circuits Syst. Video Technol. 13(7), 560–576 (2003)

      [11] Puri, A., Chen, X., et al.: Video Coding Using the H.264/MPEG-4 AVC Compression Standard. Signal Processing: Image Communication 19, 793–849 (2004)

      [12] DN-DualV6-PCIe 4User Manual, http://www.dinigroup.com/new/ DN-DualV6-PCIe-4.php

      [13] Xilinx Virtex-6 FPGA Memory Interface Solutions User GuideV3.91,http://www.xilinx.com/support/documentation/ip_documentation/ mig/v3_91/ug406.pdf

      [14] Babionitakis, K., Lentaris, G., et al.: An Efficient H.264 VLSI Advanced Video Encoder. In: 13th IEEE International Conference on Electronics, Circuits and Systems, pp. 545–548 (2006)

      [15] Chen, T.C., Chien, S.Y., et al.: Analysis and architecture design of an HDTV720p 30frames/s H. 264/AVC encoder. IEEE Trans. Circuits Syst. Video Technol. 16(6), 673– 688 (2006)

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  • How to Cite

    Raja Ramesh, D., H.S.T.Murthy, P., & B, M. (2018). FPGA based Implementation and Verification of H.264/AVC Encoder. International Journal of Engineering & Technology, 7(3.29), 737-740. https://doi.org/10.14419/ijet.v7i4.29.21649