FPGA based Implementation and Verification of H.264/AVC Encoder

  • Authors

    • D. Raja Ramesh
    • P. H.S.T.Murthy
    • Maheshwarappa B
    2018-11-26
    https://doi.org/10.14419/ijet.v7i4.29.21649
  • FPGA Prototyping, Architecture, H.264/AVC, motion estimation, HDTV.

  • Abstract

    FPGA prototyping in video processing is extremely essential as it verifies the functionality of the design. The Proposed architecture of H.264/AVC advanced video coding encoder for motion estimation is simulated, synthesized with the vivado Xilinx nexys4 DDR XC7A100TCSG324-2 field programmable gate array device hardware platform. The implemented architecture also compares with the Xilinx zynq-7000 system-on-chip (SOC) with clock frequency of 100MHz on a vivado Xilinx Artix-7 FPGA based with DDR3 memory which is compatible for real time applications for HDTV. This is suitable for high definition television applications, providing up to 60 frames 720p with PSNR around 34 db. 

     

     

  • References

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  • How to Cite

    Raja Ramesh, D., H.S.T.Murthy, P., & B, M. (2018). FPGA based Implementation and Verification of H.264/AVC Encoder. International Journal of Engineering & Technology, 7(3.29), 737-740. https://doi.org/10.14419/ijet.v7i4.29.21649

    Received date: 2018-11-26

    Accepted date: 2018-11-26

    Published date: 2018-11-26