BCD Divider Architecture For High Speed VLSI Application Using Vedic Mathematics

  • Authors

    • Rishabh S
    • Harshitha K.M
    • Prajwal R Kashyap
    • Chaitanya C V S
    • Sundaresan C
    2018-11-26
    https://doi.org/10.14419/ijet.v7i4.29.21650
  • BCD divider, Vedic technique, Nikhilam Sutra.

  • Abstract

    Power, delay, area and speed are the parameters used to evaluate any processor performance  in digital domain.  These parameters should be less to get an effective results. In all VLSI architecture, Division operation is always considered to be more complex, time consuming and bulky. Vedic Mathematics gives a new perspective to mathematics. In this paper we have implemented a BCD division architecture using Nikhilam Sutra a formula (sutra) from the vedic mathematics. Here divider has been designed to improve the results of delay using simple algorithms. The proposed designed is modeled in Verilog, simulated and synthesized using Cadence EDA tools. The proposed Vedic BCD divider performed 29.9% faster than the existing method.

     

     

  • References

    1. [1] Saha, Prabir, Arindam Banerjee, Partha Bhattacharyya, and Anup Dandapat. "Vedic divider: Novel architecture (ASIC) for high speed VLSI applications." In Electronic System Design (ISED), 2011 International Symposium on, pp. 67-71. IEEE, 2011.

      [2] Obermann, Stuart F., and Michael J. Flynn. "Division algorithms and implementations." IEEE Transactions on computers 46, no. 8 (1997): 833-854.

      [3] Ercegovac, MiloTs Dragutin, and Tomas Lang. Division and square root: digit-recurrence algorithms and implementations. Kluwer Academic Publishers, 1994.

      [4] Senapati, Ratiranjan, Bandan Kumar Bhoi, and Manoranjan Pradhan. â€Novel binary divider architecture for high speed VLSI applications.†Information & Communication Technologies (ICT), 2013 IEEE Conference on. IEEE, 2013.

      [5] Tirtha, Swami Bharati Krishna, and Vasudeva Sharana Agrawala. Vedic mathematics. Vol. 10. Motilal Banarsidass Publ., 1992.

      [6] Jain, Surabhi, and Sandeep Saini. "High speed convolution and deconvolution algorithm (Based on Ancient Indian Vedic Mathematics)." In Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2014 11th International Conference on, pp. 1-5. IEEE, 2014.

      [7] Sengupta, Diganta, Mahamuda Sultana, and Atal Chaudhuri. "An algorithm facilitating fast BCD division on low end processors using Ancient Indian Vedic Mathematics Sutras." In Communications, Devices and Intelligent Systems (CODIS), 2012 International Conference on, pp. 373-376. IEEE, 2012.

  • Downloads

  • How to Cite

    S, R., K.M, H., R Kashyap, P., C V S, C., & C, S. (2018). BCD Divider Architecture For High Speed VLSI Application Using Vedic Mathematics. International Journal of Engineering & Technology, 7(3.29), 741-743. https://doi.org/10.14419/ijet.v7i4.29.21650

    Received date: 2018-11-26

    Accepted date: 2018-11-26

    Published date: 2018-11-26