Realization and Synthesis of 4 - bit Universal Shift Register using Logical Reversible Computation in Xilinx

  • Authors

    • Gopi Chand Naguboina
    • K. Anusudha
    • T. Sravya
    2018-11-26
    https://doi.org/10.14419/ijet.v7i4.29.21656
  • Reversible logic, shift registers, universal shift registers, quantum cost, garbage outputs.

  • Abstract

    Reversible Logic is the dominating field of research in low power VLSI. In recent times reversible logic has gained special attention in order to reduce power consumption mainly in concern to digital logic design. The main aim of this paper is to realize and synthesize universal shift register using reversible logic. Universal shift register is a sequential circuit that performs all the shift operations depending upon the selection lines. Different shifting operations performed using universal shift register are Shift left operation, shift right operation, parallel loading operation and no change operation. These operations are performed by the intervention of multiplexer circuit which helps to select the mode of operation to be performed. Hence a multiplexer is also designed using reversible logic to reduce power dissipation. Shift registers has their applications in data conversions like serial to parallel and parallel to serial conversions. A Boolean function f(i1, i2, i3,……, in) having ‘n’ inputs and ‘m’ outputs is said to be logically reversible if the number of input lines are equal to the number of output lines( i.e. n = m) and the input line pattern maps uniquely the output line pattern. Few reversible logic gates in the existing literature are NOT gate, CNOT gate), Double Feynman (D2F) Gate, Peres Gate, TR gate, Seynman Gate etc. The logical reversible gates are designed such that they run both forward and backward directions and with the knowledge of output values, the input values can be also retrieved. The two limitations of logical reversibility is that Fan-out and Feed-back are not allowed. Certain output lines can be duplicated to desired number of lines using additional logical reversibly computed combinational circuits to overcome the Fan out limitation. Logical reversibility has applications in various areas like Nano- technology, optical computing, quantum computing, Computer Graphics, low power VLSI etc., Logical reversible computing has gained essence in recent times largely due to its property of low power consumption and low heat/power dissipation. In this paper, shift registers like shift right register, shift left register and universal shift registers which possess less power/heat dissipation and consumes less power is been proposed. The designed logical reversible computed circuits are analyzed in terms of quantum cost, garbage outputs and number of gates. The Circuits are been designed and simulated using Xilinx software.

     

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  • How to Cite

    Chand Naguboina, G., Anusudha, K., & Sravya, T. (2018). Realization and Synthesis of 4 - bit Universal Shift Register using Logical Reversible Computation in Xilinx. International Journal of Engineering & Technology, 7(3.29), 769-774. https://doi.org/10.14419/ijet.v7i4.29.21656

    Received date: 2018-11-26

    Accepted date: 2018-11-26

    Published date: 2018-11-26