Realization and Synthesis of 4 - bit Universal Shift Register using Logical Reversible Computation in Xilinx

  • Authors

    • Gopi Chand Naguboina
    • K. Anusudha
    • T. Sravya
    2018-11-26
    https://doi.org/10.14419/ijet.v7i4.29.21656
  • Reversible logic, shift registers, universal shift registers, quantum cost, garbage outputs.

  • Reversible Logic is the dominating field of research in low power VLSI. In recent times reversible logic has gained special attention in order to reduce power consumption mainly in concern to digital logic design. The main aim of this paper is to realize and synthesize universal shift register using reversible logic. Universal shift register is a sequential circuit that performs all the shift operations depending upon the selection lines. Different shifting operations performed using universal shift register are Shift left operation, shift right operation, parallel loading operation and no change operation. These operations are performed by the intervention of multiplexer circuit which helps to select the mode of operation to be performed. Hence a multiplexer is also designed using reversible logic to reduce power dissipation. Shift registers has their applications in data conversions like serial to parallel and parallel to serial conversions. A Boolean function f(i1, i2, i3,……, in) having ‘n’ inputs and ‘m’ outputs is said to be logically reversible if the number of input lines are equal to the number of output lines( i.e. n = m) and the input line pattern maps uniquely the output line pattern. Few reversible logic gates in the existing literature are NOT gate, CNOT gate), Double Feynman (D2F) Gate, Peres Gate, TR gate, Seynman Gate etc. The logical reversible gates are designed such that they run both forward and backward directions and with the knowledge of output values, the input values can be also retrieved. The two limitations of logical reversibility is that Fan-out and Feed-back are not allowed. Certain output lines can be duplicated to desired number of lines using additional logical reversibly computed combinational circuits to overcome the Fan out limitation. Logical reversibility has applications in various areas like Nano- technology, optical computing, quantum computing, Computer Graphics, low power VLSI etc., Logical reversible computing has gained essence in recent times largely due to its property of low power consumption and low heat/power dissipation. In this paper, shift registers like shift right register, shift left register and universal shift registers which possess less power/heat dissipation and consumes less power is been proposed. The designed logical reversible computed circuits are analyzed in terms of quantum cost, garbage outputs and number of gates. The Circuits are been designed and simulated using Xilinx software.

     

  • References

    1. [1] R. Landauer, ―Irreversibility and Heat Generation in the Computational Process‖, IBM Journal of Research and Development, 5, pp. 183- 191, 1961.

      [2] C.H. Bennett, ―Logical Reversibility of Computation‖, IBM J.Research and Development, pp. 525-532, November 1973.

      [3] C H Bennett, "Notes on the History of Reversible Computation", IBM Journal of Research and Development,vol. 32, pp. 16-23, 1998.

      [4] R. Feynman,‖quantum mechanical computers:, Optic News, vol. 11,pp 11-20, 1985.

      [5] A. Peres, ―Reversible logic and quantum computers‖, phys.rev.A,Gen.Phys., vol. 32, no. 6, pp. 32663276, Dec. 1985.

      [6] H.G Rangaraju, U. Venugopal, K.N. Muralidhara, K. B. Raja,‖Low power reversible parallel binary adder/subtractor‖ arXiv.org/1009.6218,2010.

      [7] J.M. Rabaey and M. Pedram, ―Low Power Design Methodologies,‖ Kluwer Academic Publisher, 1997.

      [8] T. Toffoli., ―Reversible Computing‖, Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science 1980.

      [9] Y. Syamala, and A. V. N. Tilak, ―Reversible Arithmetic Logic Unit‖, Electronics Computer Technology (ICECT), 2011 3rd International, vol. 5, pp.207-211,07 july 2011.

      [10] Thapliyal H, Ranganathan N.,‖ Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs‖ Centre for VLSI and Embedded .

      [11] V.Rajmohan, V.Ranganathan,‖Design of counter using reversible logic‖ 978-1-4244-8679-3/11/$26.00 ©2011 IEEE.

      [12] Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, and John P. Hayes,‖ Synthesis of Reversible Logic Circuits‖, IEEE Transaction on computer-aided design of integrated circuits and systems, vol. 22, No. 6, June 2003.

      [13] Payal Garg, Sandeep Saini,"A novel design of compact reversible SG gate and its applications‖,2014 14th International Symposium on Communications and Information Technologies(ISCIT), Sept 2014, pages 400-403, doi: 10.1109/ISCIT.2014.7011941

      [14] V. Rajmohan, V. Ranganathan, “Design of counters using reversible logicâ€, 3rd International Conference on Electronics Computer Technology, 978-1-4244-8679- 3/11/$26.00 ©2011 IEEE.

      [15] Shefali Mamataj, Biswajit Das, Saravanam Chandran, “An Approach for Designing of Sequence Generator by Counter and Multiplexer of Reversible Gatesâ€, International Conference on Contemporary Computing and Informatics – (IC3I – 2014), 978-1-4799-6629-5/14/$31.00_c 2014 IEEE.

      [16] Shefali Mamataj, Biswajit Das, “Efficient Designing Approach of Different Synchronous Cyclic Code Counters by Sequential Circuits Elements of a Novel Reversible Gateâ€, Sixth International Conference on Computational Intelligence and Communication Networks†- (ICCICN – 2014) ,978-1-4799-6929-6/14 $31.00 © 2014 IEEE.

      [17] D.Santhiya, D.N.Keerthi Kumar, “Testable Circuit for Universal Shift Register Using Reversible Gatesâ€,International Journal for Innovative Research and studies,ISSN 2319-9725,Volume3, Issue5, may 2014.

      [18] Jadav ChandraDas, Debashis De and Tapatosh Sadu.‖ A novel low power nano scale reversible decoder using quantum dot cellular automata for nano communication‖, Third International Conferrence on devices, circuits and systems, 2016.

      [19] Ritjit Maumdar, sandeep saini ― A novel design of reversible 2: 4 decoder‖,978-1-4799-6761-2/$31.00©2015 IEEE

      [20] Rupali Singh, Manoj Kumar Pandey, “Design and Optimization of Sequential Counters Using A Novel Reversible Gateâ€, International Conference on Computing Communication and Automation†–(ICCCA - 2016), 978-1-5090-1666-2/16/$31.00 ©2016 IEEE.

      [21] Gopi Chand Naguboina, K. Anusudha, “Design and synthesis of combinational circuits using reversible decoder in Xilinx†– International Conference on Computer, Communication and Signal Processing (ICCCSP -17) , 978-1-5090-3716-2/17/$31.00 ©2017 IEEE.

      [22] Gopi Chand Naguboina, K. Anusudha, “Design and Implementation of Programmable Read Only Memory using reversible decoder on FPGA†– International Conference on Signal Processing, Communications and Networking, (ICSCN – 17), 978-1-5090-4740-6/17/$31.00 ©2017 IEEE.

      [23] Gopi Chand Naguboina, K. Anusudha, “Design and Implementation of PAL and PLA using Reversible Logic on FPGA Spartan 3E†– International Conference on Signal Processing, Communications and Networking (ICSCN - 2017), 978-1-5090-4740-6/17/$31.00 ©2017 IEEE.

      [24] Gopi Chand Naguboina, K. Anusudha, “Design and Implementation of BCD to Seven Segment Display Decoder using reversible decoder on FPGAâ€, International Journal of Computing and Applications, Volume 13, Number 2, (March - April 2018), pp 265-275© Serials Publications, New Delhi (India), ISSN: 0973-5704.

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    Chand Naguboina, G., Anusudha, K., & Sravya, T. (2018). Realization and Synthesis of 4 - bit Universal Shift Register using Logical Reversible Computation in Xilinx. International Journal of Engineering & Technology, 7(3.29), 769-774. https://doi.org/10.14419/ijet.v7i4.29.21656