Performance Analysis and Low Power Design of Voltage Level-up Shifters

  • Authors

    • B. Srikanth
    • Rameswari Nayak
    • Sangeeta Singh
    • V. Harini
    2018-11-27
    https://doi.org/10.14419/ijet.v7i4.19.22022
  • Current mirrors, Dual supply voltages, Level-up shifter, Process variation, Sub threshold operation.

  • Abstract

    Voltage level-up shifters are widely used in dual supply applications and it acts as an interface between main core and input-output units. Low power with efficient level-up shifter is designed by reducing the transistor count and the proposed level-up shifters are capable of converting from sub-threshold to above threshold level signal. The strength of pull-down networks and pull-up networks are enhanced by employing a couple of current mirror circuits. The simulation results of the proposed level shifter in 180nm technology yields a power dissipation of 95.79nw, propagation delay of 41.23ns for an input voltage of 0.4V and input frequency of 1MHz, low supply voltage VDDL=0.4V, high supply voltage VDDH=1.8V. Proposed 14T Level shifter in 90nm Technology demonstrates a power dissipation of 54.8nw, propagation delay of 28.8ns for an input voltage of 0.2V and input frequency of 1MHz, VDDL=0.2V, VDDH=1.2V.

     

     

  • References

    1. [1] A. Wang and A. P.Chandrakasan, “A 180-mV sub threshold FFT processor using a minimum energy design methodology,†IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310–319, Jan. 2005

      [2] K. Usami, M. Igarashi, F. Minami, T. Ishikawa, M. Kanazawa, M. Ichida, and K. Nogami,, “Automated low-power technique exploiting multiple supply voltages applied to a media processor,†IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 463–472, Mar. 1998.

      [3] Padmapriya Kesari, “A Novel Energy Efficient Transmission Gate Voltage Level Shifter for multi VDD systems,†International Journal of scientific research and management (IJSRM), vol.3, pp.2263-2266, Mar.2015.

      [4] D. Zhang, A. Bhide, and A. Alvandpour, “A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices,†IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1585–1593, Jul. 2012.

      [5] Manoj Kumar, Sandeep K.Arya, Sujata Pandey, “Level shifter design for low power applications,†IJCSIT, vol.2, no.5, pp.124-132, Oct. 2010.

      [6] Jan M. Rabaey, Anantha Chandrakasen, Borivoje Nikolic, “Digital Integrated Circuits- A Design Perspective,†4th Edition, Pearson Publications.

      [7] Fujio Ishihara, Farhana Sheikh,and Borivoje Nikolic, “ Level Conversion for Dual-Supply Systemsâ€, IEEE transactions on very large scale integration (VLSI) systems, vol. 12, no. 2, Feb. 2004.

      [8] Canh Q. Tran, Hirosh Kawaguchi and Takayasu Sakurai, “Low-power High-speed Level Shifter Design for Block-level Dynamic Voltage Scaling Environmentâ€, IEEE International Conference on Integrated Circuit and Technology, vol. 05, pp. 229-232, Mar. 2005.

      [9] S. Lutkemeier and U. Ruckert, “A subthreshold to above-threshold level shifter comprising a Wilson current mirror,†IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 9, pp. 721–724, Sep. 2010.

      [10] S.C. Luo, C.J. Huang, and Y.H. Chu, “A wide-range level shifter using a modiï¬ed Wilson current mirror hybrid buffer,†IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 6, pp. 1656–1665, May 2014.

      [11] S. R. Hosseini, M. Saberi, and R. Lotï¬, “A low-power sub-threshold to above-threshold voltage level shifter,†IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 10, pp. 753–757, Oct. 2014.

      [12] Gray. Hurst, Lewis. Meyer, “Analysis and Design of Analog Integrated circuits,†5th Edition, Wiley Publications.

      [13] S. R. Hosseini, M. Saberi, and R. Lotï¬, “A high-speed and power efï¬cient voltage level shifter for dual-supply applications,†IEEE Trans. Very Large Scale Integration. (VLSI) Systems, vol. 25, no. 3, pp. 1154–1158, Mar. 2016.

      [14] Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, and Jianyi Meng, “An Energy-Efï¬cient and Wide-Range Voltage Level Shifter with Dual Current Mirror,†IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-5, Aug.2017. Doi. 10.1109 /TVLSI.2017.2748228.

  • Downloads

  • How to Cite

    Srikanth, B., Nayak, R., Singh, S., & Harini, V. (2018). Performance Analysis and Low Power Design of Voltage Level-up Shifters. International Journal of Engineering & Technology, 7(4.19), 76-82. https://doi.org/10.14419/ijet.v7i4.19.22022

    Received date: 2018-11-28

    Accepted date: 2018-11-28

    Published date: 2018-11-27