Diminished-1 multiplier using modulo adder

  • Authors

    • Beerendra Kumar Patel
    • Jitendra Kanung
    2018-11-28
    https://doi.org/10.14419/ijet.v7i4.20.22117
  • Residue number system, computer arithmetic, diminished-1 representation, modulo 122n 1"> adders.

  • Abstract

    In this work Modulo multiplier offers higher computational speed than a normal multiplier. It is frequently used in data security and residue number system. The modulo 122n+1">   has three basic blocks-partial product generation block, inverted end around carry adder tree block and diminished-1 modulo 122n+1">   adder block. The result and an operand use weighted representation and others uses the diminished-1 for the modulo multiplier. The multipliers receive full inputs and avoid (n+1) bits circuits due to diminished-1 number representation. In this work, proposed modulo 122n+1">  multiplier with modified diminished-1 modulo 122n+1">   adder which is based on ripple carry adder. The proposed design saves significant area and power as compared to the reported one with little increment in delay.

     

     

  • References

    1. [1] P. V. A. Mohan,Residue Number Systems: Algorithms and Architectures, Norwell, MA: Kluwer(2002).

      [2] R. Zimmermann, A. Curiger, H. Bonnenberg, H. Kaeslin, N. Felber, and W. Fichtner, “A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm,†IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 303–307(1994).

      [3] J. Ramirez, A. Garcia, S. Lopez-Buedo, and A. Lloris “RNS Enabled digital signal processingâ€, Electronics Letters, vol. 38, no. 6, pp. 226-268,(2002)

      [4] Y. Kong and Braden, “Fast scaling in the residue number system,†IEEE Trans. VLSI Syst., vol. 17, pp. 443–447(2009).

      [5] Curiger, H. Bonnenberg, and H. Kaeslin,“Regular VLSI architecture for multiplication modulo 122n+1 "> ,â€IEEE J. solid state circuits, vol. 26, no. 7, pp. 990-994(1991).

      [6] Z. Wang, G. A. Jullien, and W. C. Miller, “An efficient tree architecture for modulo 12 2n+1 "> multiplication,†J. VLSI Signal Process. Syst., vol. 14, no. 3, pp. 241–248(1996).

      [7] R. Zimmermann,“Efficient VLSI implementation of modulo addition and multiplication,†in Proc. 14th IEEE Symp. Comput. Arithm., Adelaide, Australia, pp. 158–167(1999).

      [8] L. Sousa and R. Chaves, “A universal architecture for designing efficient modulo 122n+1 "> multipliers,†IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 6, pp. 1166–1178(2005).

      [9] C. Efstathiou, H. T. Vergos, G. Dimitrakopoulos, and D. Nikolos, “Efficient diminished-1 modulo 122n+1 "> multipliers,†IEEE Trans. Comput., vol. 54, no. 4, pp. 491–496(2005).

      [10] H. T. Vergos and C. Efstathiou , “Design of efficient modulo 122n+1 "> multipliers,†IET Comput. Digit. Tech., vol. 1, no. 1, pp. 49–57(2007).

      [11] J.W. Ruo, R. H. Tao and W.J. Wu, “Efficient modulo 122n+1 "> multiplier,â€IEEE Trans. VLSI system, Vol.19,No.19(2011).

      [12] H. T. Vergos, C. Efstathiou, and D. Nikolos, “Diminished-one modulo 122n+1 "> adder design,†IEEE Trans. Comput., vol. 51, no. 12, pp. 1389–1399(2002).

      [13] H. T. Vergos and C. Efstathiou, “A unifying approach for weighted and diminished-1 modulo addition,†IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 10, pp. 1041–1045(2008).

  • Downloads

  • How to Cite

    Kumar Patel, B., & Kanung, J. (2018). Diminished-1 multiplier using modulo adder. International Journal of Engineering & Technology, 7(4.20), 31-35. https://doi.org/10.14419/ijet.v7i4.20.22117

    Received date: 2018-11-28

    Accepted date: 2018-11-28

    Published date: 2018-11-28