Efficient Hardware Design of In-Loop Filter for High-Performance HEVC Encoder

  • Authors

    • Seungyong Park
    • Kwangki Ryoo
    https://doi.org/10.14419/ijet.v7i3.24.22531
  • HEVC, In-Loop filter, Deblocking filter, SAO, Hardware design

  • Abstract

    Background/Objectives: An HEVC encoder consists of an in-loop and deblocking filter. In this paper, we propose an efficient in-loop filter hardware architecture for high performance HEVC encoder.

    Methods/Statistical analysis: The proposed in-loop filter hardware structure is divided into deblocking filter, SAO, and in-loop filter scheduler. The proposed deblocking filter uses an internal line buffer to reduce the overhead of external memory access in order to minimize hardware footprint. SAO has a high throughput with a 4x4 block size unit operation. It uses minimal hardware area by simplifying the equation used to determine the offset value.

    Findings: The in-loop filter hardware structure of the HEVC encoder proposed in this paper is synthesized at 260MHz with 90nm cell library, and it is possible to process 262.78K gates and 8K@120Fps in real time.

    Improvements/Applications: The proposed in-loop filter hardware architecture can be applied to high-performance HEVC video codec hardware, and it can be used as an individual filter because of in-loop filter characteristics.

     

     

  • References

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  • How to Cite

    Park, S., & Ryoo, K. (2018). Efficient Hardware Design of In-Loop Filter for High-Performance HEVC Encoder. International Journal of Engineering & Technology, 7(3.24), 176-184. https://doi.org/10.14419/ijet.v7i3.24.22531

    Received date: 2018-11-30

    Accepted date: 2018-11-30