Hardware Design of AES Core with High Throughput and Low Area

  • Authors

    • Alexander Owusu-Ansah Antwi
    • Kwangki Ryoo
    https://doi.org/10.14419/ijet.v7i3.24.22659
  • On-the-fly key generation, ASIC, Encryption, Decryption, CMOS, Sub-pipelined architecture

  • Abstract

    Background/Objectives:  The Advanced Encryption Standard is currently the most used algorithm for symmetric encryption. In this paper, we propose a hardware architecture of AES with an improved key generation unit.

    Methods/Statistical analysis: We employ the use of a four-stage sub-pipelined architecture for encryption and decryption of all standard key sizes (128, 192 and 256 bits) of the Advanced Encryption Standard (AES). The implementation features an LUT-based S-Box as well as on-the-fly key generation. The RTL of the architecture was designed using Verilog HDL and simulated with ModelSim. The verified design was then synthesized in Synopsis Design Compiler with 180nm TSMC cell libraries.

    Findings: Since the inception of AES, many implementations have been done in both software and hardware. For the purpose of robustness, the hardware implementation is much preferred. However, for area-constrained implementations, it is necessary for designers to present a very small area of the AES algorithm while keeping the AES structure and security unchanged. The proposed compact key generation unit contributed to the small area of 21.3K equivalent NAND2 gates. The S-Box was implemented as a ROM of size 9.152KB. In order to match the encryption/decryption, the on-the-fly also key generation was accordingly made to output round keys every four cycles. With this structure, there was a high average throughput yield of 11.51Gb/s, 9.75Gb/s and 8.46Gb/s for the 128-bit, 192-bit and 256-bit key lengths respectively, corresponding to a maximum frequency of 1GHz.

    Improvements/Applications: In the future, we will investigate more techniques to reduce the area of the S-Box and Mix Column structures. We will implement the design on an SoC system for verification and testing.

     

  • References

    1. [1] CSO online. The 17 biggest data breaches of the 21st century. https://www.csoonline.com/article/2130877/data-breach/the-biggest-data-breaches-of-the-21st-century.html. Revised January 2. Accessed September 2, 2018.

      [2] Shastry PVS, Kulkarni A & Sutaone MS (2012), ASIC implementation of AES. Proceedings of the 2012 Annual IEEE India Conference (INDICON) 1255-1259.

      [3] Cao Q & Li S (2009), A high-throughput cost-effective ASIC implementation of the AES Algorithm. Proceedings of the 2009 IEEE 8th International Conference on ASIC 805-808.

      [4] Tales from the Crypt: Hardware vs Software [Internet]. Infosecurity group. 2015. [updated 2015 June 23; cited 2018 Aug 31] Available from: https://www.infosecurity-magazine.com/magazine-features/tales-crypt-hardware-software

      [5] Gaj K & Chodowiec P (2009) Cryptography Engineering: FPGA and ASIC Implementations of AES. Boston: Springer US;

      [6] Saravanan P, Devi RN, Swathi G & Kalpana P (2011), A High-Throughput ASIC implementation of Configurable Advanced Encryption Standard (AES) Processor. International Journal of Computer Applications (IJCA) 3, 1-6.

      [7] Advanced Encryption Standard. https://en.wikipedia.org/wiki/Advanced_Encryption_Standard. Revised August 25. Accessed September 2, 2018.

      [8] Rijmen V & Daemen, J (2002) The design of Rijndael: AES-The Advance Encryption Standard. Berlin: Springer-Verlag.

      [9] Paar C & Pelzl J (2010) Understanding Cryptography. Berlin Heidelberg: Springer-Verlag.

      [10] Li H (2006), Efficient and flexible architecture for AES. IEE Proceedings - Circuits, Devices and Systems 153, 533-538.

      [11] Dao VL, Nguyen AT, Hoang VP& Tran TA (2015), An ASIC implementation of low area AES encryption core for wireless networks. Proceedings of the 2015 International Conference on Communications, Management and Telecommunications (ComManTel) 99-102.

      [12] López RL, García ML & Navarro EC (2018), Hardware Architecture Implemented on FPGA for Protecting Cryptographic Keys against Side-Channel Attacks. IEEE Transactions on Dependable and Secure Computing 15, 898-905.

      Kalaiselvi K & Mangalam H (2015) Power efficient and high-performance VLSI architecture for AES algorithm. Journal of Electrical Systems and Information Technology 2, 178-183.

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  • How to Cite

    Owusu-Ansah Antwi, A., & Ryoo, K. (2018). Hardware Design of AES Core with High Throughput and Low Area. International Journal of Engineering & Technology, 7(3.24), 258-263. https://doi.org/10.14419/ijet.v7i3.24.22659

    Received date: 2018-12-01

    Accepted date: 2018-12-01