ASIC Design of Low Area RSA Crypto-core based on Montgomery Multiplier

  • Abstract
  • Keywords
  • References
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  • Abstract

    Background/Objectives: Currently, the most popular public key encryption is RSA. We present a low area hardware design of RSA crypto-core based on the Montgomery algorithm in ASIC.

    Methods: We employed Carry Save Adder in the design of the multiplier which plays a critical role in the overall design. The proposed hardware was designed at Register Transfer Level using Verilog description language with Xilinx 14.3 ISE design suite and simulated with ModelSim. In ASIC implementation, TSMC 90nm and 130nm CMOS technology was employed for synthesis of the Montgomery multiplier and modular exponentiation respectively.

    Findings: The primal operation of RSA cryptosystem is modular exponentiation, computed by repetitions of modular multiplications. Fast modular multiplication algorithms over the years have been proposed to speed up exponentiation and yet maximize performance. The core of this paper evolved from the modification of the modified Montgomery multiplication algorithm. From the new algorithm, a hardware architecture which simplifies the operation of the Q_logic coupled with a compact two-level CSA in the Montgomery multiplier is designed. The simplified Q_logic design and the elimination of traditional BRFA and bypass circuitry accounted for a reduction in area. Furthermore, the new multiplier is applied in the H-algorithm to develop the modular exponentiation unit. Other relevant modules in the RSA crypto-core including the pseudorandom number generator, primality tester and key generator have been optimized for resource sharing to balance and improve speed and area of the system. Synthesis results of the proposed multiplier and exponentiation unit achieved a gate count of 60K and 79K representing a reduction of 47% and 28% respectively.

    Improvement/Applications: Our system is suitable for low area RSA applications. Future works on this paper will examine the analysis and design of Carry Save Adder to improve propagation delay.



  • Keywords

    Fublic key cryptosystem, Carry Save Adder (CSA), RSA, Montgomery multiplication, Barrel Register Full Adder (BRFA), Modular exponentiation.

  • References

      [1] Nayak SK, Mohanty S, Majhi B (2017), CLB-ECC: Certificateless blind signature using ECC. J. Information Processing Systs. 13, 970–986.

      [2] Rivest L, Shamir A, Adleman L (1978), A method for obtaining digital signatures and public-key cryptosystems. Comm. ACM 21, 120–126.

      [3] Koblitz N (1987), Elliptic curve cryptosystems. Math. Comput. 48, 203–209.

      [4] Montgomery PL (1985), Modular multiplication without trial division. Math. Comput. 44, 519–521.

      [5] Kim YS, Kang WS, Choi JR (2000), Asynchronous implementation of 1024-bit modular processor for RSA cryptosystem. Proc. 2nd IEEE Asia-Pacific Conf. ASIC, 187–190.

      [6] Zhang YY, Li Z, Yang L, Zhang SW. (2007), An efficient CSA architecture for Montgomery modular multiplication. Microprocessors Microsyst. 31, 456–459.

      [7] Kuang SR, Wang JP, Chang KC, Hsu HW (2013), Energy-efficient high-throughput Montgomery modular multipliers for RSA cryptosystems. IEEE Trans. Very Large Scale Integration (VLSI) System 21, 1999–2009

      [8] McIvor C, McLoone M, McCanny JV (2004), Modified Montgomery modular multiplication and RSA exponentiation techniques. IEE Proc. Comput. Digit. Techn. 151, 402–408

      [9] Koç ÇK (1994), High-speed RSA implementation. Technical Report, RSA Laboratories, RSA Data Security Inc., 46–49.

      [10] Daly A, Marane W (2002), Efficient architectures for implementing Montgomery modular multiplication ad RSA modular exponentiation on reconfigurable logic. Proc. of the 2002 ACM/SlGDA 10th international symposium on FPGA ACM, 40–49

      [11] Walter CD (1999), Montgomery exponentiation needs no final subtractions. Electronics Letters Journal 35, 1831–1832

      [12] Hu ZB, Shboul RMA, Shirochin VP (2007), An efficient architecture of 1024-bits cryptoprocessor for RSA cryptosystem based on modified Montgomery’s algorithm. Proc. 4th IEEE Int. Workshop Intell Data Acquisit. Adv. Comput. System, 643–646

      [13] Kuang SR, Wu KY, Lu RY (2016), Low-cost high-performance VLSI architecture for Montgomery modular multiplication. IEEE Trans. Very Large Scale Integration (VLSI) System 24, 440-442.

      [14] Martín H, Millán ES, Entrena L, Castro JCH, López PP (2011), AKARI-X: a pseudorandom number generator for secure lightweight systems. IEEE 17th Conf. On-Line Testing Symposium.

      [15] Miller GL (1976), Riemann’s hypothesis and tests for primality. J. Comput. Syst. Sci. 13, 300–317.

      [16] Rabin MO (1980), Probabilistic algorithm for testing primality. J. Number Theory 12, 128–138.

      [17] Shieh MD, Chen JH, Wu HH, Lin WC (2008), A new modular exponentiation architecture for efficient design of RSA cryptosystem. IEEE Trans.Very Large Scale Integration (VLSI) System 16, 1151–1161.

      [18] Mallick PK, Kamila NK (2011), Crypto steganography using linear algebraic equation. Int. J. Comput. Comm. Techn. 2, 106–112.

      [19] Mallick PK, Kamila NK, Patnaik S (2011), Computing symmetric block cipher using linear algebraic equation. Int. J. Comm. Net. Sec. 1, 7–11.




Article ID: 22663
DOI: 10.14419/ijet.v7i3.24.22663

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