Implementation of Deep Learning based Rendering De-Noising Accelerator
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https://doi.org/10.14419/ijet.v7i3.24.22834
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Ray tracing, Rendering noise, Leaning based filtering, Neural network, FPGA, MLP -
Abstract
Background/Objectives: In this paper, we implemented the neural network of learning based filtering algorithm, which eliminates noise generated by ray-tracing, through Verilog HDL.
Methods/Statistical analysis: The neurons used in the learning based filtering algorithm are divided into five stages: IDLE, SIGN, MUL, SUM, and ACT. Each stage is processed in one cycle through the FSM(Finite State Machine).These neurons were organized into a number of layers. The operation used fixed point.
Findings: The neural network has a large amount of computation, but since the computation is simple, it can be processed quickly by hardware implementation. It has a hidden layer (10 neurons with 36 inputs), an output layer (6 neurons with 10 inputs), each layer has 5 stages, so you can get the filtering parameters after 10 cycles.
Improvements/Applications: Verilog HDL can be synthesized and downloaded to the FPGA to operate up to 185MHz.
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References
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How to Cite
Han, S.-H., & Lee, K.-Y. (2018). Implementation of Deep Learning based Rendering De-Noising Accelerator. International Journal of Engineering & Technology, 7(3.24), 651-654. https://doi.org/10.14419/ijet.v7i3.24.22834Received date: 2018-12-02
Accepted date: 2018-12-02