Design and Implementation of Low Power, Area Efficient Full Adder for High Performance Digital Circuit Applications

  • Authors

    • M. Kathirvelu
    • Hima Bindu
    https://doi.org/10.14419/ijet.v7i3.20.22946
  • Low power, Full Adder, XOR- XNOR GATE, Multiplier.

  • Abstract

    Design and implementation of low power, low delay and area efficient full adder using new architecture of XOR-XNOR gates will be efficient than existing full adders. Design of hybrid 1-bit full adder circuits combined in a single circuit employing both complementary metal-oxide-semiconductor (CMOS) logic and transmission gate logic. The proposed architecture will consume less power consumption, transistor area and propagation delay and it is compared with existing design such as Complementary Pass Transistor Logic [CPL], Transmission Gate Full Adder [TGA], Transmission Function Adder [TFA], SERF and 14T full adder. Use of proposed adder, 8-bit array multiplier is designed and its performance is compared with CMOS architecture. The simulation of all designed structure is performed in Cadence Virtuoso Tools in 90-nm technology

     

     

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  • How to Cite

    Kathirvelu, M., & Bindu, H. (2018). Design and Implementation of Low Power, Area Efficient Full Adder for High Performance Digital Circuit Applications. International Journal of Engineering & Technology, 7(3.20), 584-587. https://doi.org/10.14419/ijet.v7i3.20.22946

    Received date: 2018-12-02

    Accepted date: 2018-12-02