Design a Glitch Tolerant Adiabatic Dynamic Logic Circuits for Cryptography

  • Authors

    • A. Naga Ganesh
    • Michael Cholines Pedapudi
    • N. V. Apparao
    • . .
    2018-11-27
    https://doi.org/10.14419/ijet.v7i4.19.23173
  • Parallel Prefix Adder, Ripple carry adder, carry save adder (CSA), Field-Programmable-Gate-Array (F.P.G.A), Digital Signal Processing (DSP), Look Up Table (LUT).

  • Abstract

    Adiabatic logic design is an efficient superconductor logic which performs adiabatic switching operation. The Adiabatic logic is the most essential part of the variable latency design.  The design of conventional CMOS logic circuit depends on the charging of output capacitive nodes. Here a glitch tolerant adiabatic design logic is proposed. For stumpy power applications, although there are many ‘techniques’ mutually at way level and system stage. To reduce the power consumption, the charging of capacitive nodes should process the operating part in slow manner.  From this it can observe that it takes less amount of energy to charge the capacitive nodes. Several Adiabatic designs have been proposed in literature. Most of them achieve significant power savings in comparison to conventional circuits. From the proposed glitch tolerant logic design it can observe that by performing adiabatic switching operations there is a reduction in dynamic energy dissipation. To minimize this switching power we use a factoring technique in adiabatic logic. The main drawback is that it uses junction diodes for controlling the charging and discharging of output nodal capacitance. Junction diodes are difficult to fabricate in a CMOS process. From this it can observe that the compared to existed system proposed system gives effective results.

     

     

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  • How to Cite

    Naga Ganesh, A., Cholines Pedapudi, M., V. Apparao, N., & ., . (2018). Design a Glitch Tolerant Adiabatic Dynamic Logic Circuits for Cryptography. International Journal of Engineering & Technology, 7(4.19), 402-406. https://doi.org/10.14419/ijet.v7i4.19.23173

    Received date: 2018-12-05

    Accepted date: 2018-12-05

    Published date: 2018-11-27