Design a High Speed Parallel Prefix Adder using Generator and Propagator

  • Authors

    • Gajula Lakshminarayana
    • Anupama A.Deshpande
    • Moparthy Gurunadha Babu
    2018-11-27
    https://doi.org/10.14419/ijet.v7i4.19.23178
  • Parallel Prefix Adder, Ripple carry adder, carry save adder (CSA), Field Programmable Gate Array (FPGA), Digital Signal Processing (DSP), Look Up Table (LUT).
  • Basically, Adders are used in VLSI designs. The chip packaging techniques are used in low power circuits which increases the design cost. Here a parallel prefix adder is proposed which is a rudimentary purposeful element in greatest computational stages and produces high performance. Parallel prefix adder is mostly classified hooked on3phases which are  pre-computation, precede then  post  subtraction.  While operating in the sub-threshold regime the proposed system gives effective results. In parallel prefix adder the addition process is done by adding the bits in parallel. The speed of parallel operation decides the computational operation. The Parallel prefix adder is used to avoid the high power consumption obtained in the system. Parallel prefix adder are derivative after the transmit appearance ahead adders. The delay gets reduced by achieving low logical depth in the system.  So the Proposed Adder reduces the delay. Compared to wave carry adding machine besides convey except calculator, similar preface adder gives better results. It is implemented on Xilinx 14.7 and delay measurements are done.

     

     

  • References

    1. [1] Pakkiraiah. Chakali, madhu Kumar. Patnala “Design of high speed Brent - Kung based carry select adder†IJSCE, Volume-3, Issue-1, march 2013

      [2] HaridimosT.Vergos, Member, IEEE and Giorgos Dimitrakopoulos, Member, IEEE,†On modulo 2n+1 adder design†IEEE Trans on computers, vol.61, no.2, Feb 2012

      [3] David h, k hoe, Chris Martinez and Sri Jyothsnavundavalli “Design and characterization of parallel prefix adders using FPGAs“, Pages.168-172, march2011 IEEE.

      [4] K. Vitoroulis and A.J. Al-Khalili, “performance of parallel prefix adders implemented with FPGA technology,†IEEE Northeast Workshop on circuits and systems, pp.498-501, Aug 2007.

      [5] GiorgosDimitrakopoulos and DimitrisNikolos, “High Speed Parallel Prefix ...Ling adders," IEEE Transactions on Computers, vol.54, no.2, February 2005

      [6] S. Knowles,†A family of adders,â€proc.15thsymp. Comp. Arith, pp. 277-281, June 2001.

      [7] R.Brent and H.Kung,“Aregularlayoutforparallel adders,†IEEETrans.Computers, vol.C-31,no.3, pp. 260-264,March1982.

      [8] R.E. Brent and M.J. Kung, “Parallel Prefix Computation,†J. ACM, vol. 27, no. 4, pages 831-838, Oct. 1980.

      [9] R. P Brent and H. T. Kung, “A Regular Layout for Parallel Adders,†in IEEE Trans. Computers, Vol. C-31, pp. 260-264,1982.

      [10] B. Ramkumar and H. M. Kittur, "Low-Power and Area Efficient Carry Select Adder," in IEEE Transactions on Very Large Scale Integration (Visi) Systems, Vol. 20, No. 2, February 2012.

      [11] P. Kogge and H. Stone, “A parallel algorithm for the efficient solution of general class Recurrence equations,†in IEEE Trans. Computers, Vol.C-22, pp. 786-793, Aug. 1973.

      [12] M. Sunil, R.D. Ankith, G.D. Manjunatha and B.S. Premananda, “Design and implementation of faster parallel prefix kogge stone adder,†in International Journal of Electrical and Eletronic engineering and Telecommunications, ISSN. 2319 –2518 Vol. 3, No. 1, January 2014.

      [13] JasbirKaur and LalitSood, “Comparison between various types of adder topologies,†in IJCST, ISSN 2229 – 4333 Vol. 6, No. 1, March 2015.

      [14] R. Ladner and M. Fischer, “Parallel prefix computation,†in Journal of ACM.La. Jolla CA, Vol.27, pp. 831-838, October1980.

      [15] V. Ionescu, I. Bostan, and L. Ionescu, “Systematic Design for Integrated Digital Circuit Structures,†in IEEE Journal of Semiconductor Conference, Vol.2, pp. 467 – 470, 2004.

  • Downloads

  • How to Cite

    Lakshminarayana, G., A.Deshpande, A., & Gurunadha Babu, M. (2018). Design a High Speed Parallel Prefix Adder using Generator and Propagator. International Journal of Engineering & Technology, 7(4.19), 430-434. https://doi.org/10.14419/ijet.v7i4.19.23178