Design a High Speed Parallel Prefix Adder using Generator and Propagator

Abstract

Basically, Adders are used in VLSI designs. The chip packaging techniques are used in low power circuits which increases the design cost. Here a parallel prefix adder is proposed which is a rudimentary purposeful element in greatest computational stages and produces high performance. Parallel prefix adder is mostly classified hooked on3phases which are  pre-computation, precede then  post  subtraction.  While operating in the sub-threshold regime the proposed system gives effective results. In parallel prefix adder the addition process is done by adding the bits in parallel. The speed of parallel operation decides the computational operation. The Parallel prefix adder is used to avoid the high power consumption obtained in the system. Parallel prefix adder are derivative after the transmit appearance ahead adders. The delay gets reduced by achieving low logical depth in the system.  So the Proposed Adder reduces the delay. Compared to wave carry adding machine besides convey except calculator, similar preface adder gives better results. It is implemented on Xilinx 14.7 and delay measurements are done.