Investigation of 6T SRAM Characteristics Using TFET

  • Authors

    • Jency Rubia J
    • Babitha Lincy R
    • . .
    https://doi.org/10.14419/ijet.v7i3.34.25344
  • Buffer, CMOS, Hetero junction, SRAM read/write, SRAM, TFET.
  • This paper proposes to design and investigate the SRAM memory cell features using TFET in the InAs/GaSb-InAs platform. This platform lies within the type III (Hetero-junction) alignment in TFET. The word TFET symbolizes to the Tunneling Field Effect Transistor which is related to the MOSFET but follows quantum tunneling switching mechanism. TFET having an advantage over MOSFET such as high speed, energy efficient and low power applications in the field of integrated circuits. The suggested project is the design of 6T SRAM memory cell with 32nm TFET technology. Finally, the performance estimation of the proposed SRAM has been compared with CMOS, FinFET, and CNFET. The study of the competence of the SRAM cell can be done by Hspice tool and Verilog-A language used.

     

     

  • References

    1. [1] Hao Lu and Alan Seabaugh, “Tunnel Field-Effect Transistors: State of the Art,†Journal of the Electron Devices Society, Vol 2, No 4, July 2014.

      [2] Sung Hwan Kim et al, “ Tunnel Field Effect Transistor with Raised Germanium Source,†IEEE Electron Device Letters, Vol 31, No 10,October 2010.

      [3] Yingxin Qiu et al, “ A Comparative Study on the Impacts of Interface Traps on Tunneling FET and MOSFET,†IEEE Transactions on Electron Devices, Vol 61, No 5, May 2014.

      [4] S. Richter et al, “Tunnel FET Inverters for Ultra Low Power Logic with Supply Voltage down to =0.2 V,†International Conference on Ultimate Integration on Silicon (ULIS), April 2014.

      [5] Siyuranga O et al, “Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs,†IEEE Transactions on Electron Devices, Vol 56, No 3, March 2009.

      [6] MinJin Lee and Woo Young Choi, “Dependency of Tunneling Field-Effect Transistor (TFET) Characteristics on Operation Region,†Journal of Semiconductor Technology and Science, Vol 11, No 4, December 2011.

      [7] Thomas Nirschl et al, “The Tunneling Field Effect Transistor: The Temperature Dependence, The Simulation Model, and its Applications,†IEEE International Symposium on Circuits and Systems, September 2004.

      [8] Adam Makosiej et al, “A 32nm Tunnel FET SRAM for Ultra Low Leakage,†IEEE International Symposium on Circuits and Systems, August 2012.

      [9] Ashwin S Raj, Sreejith S and Sajeshkumar U, “TCAD Design of Tunnel FET Structures and Extraction of Electrical Characteristics,†International Journal of Science and Research, Vol 4, No 7, July 2015.

      [10] Joao A Marino et al, “Field Effect Transistors: From Mosfet to Tunnel-FET Analog Performance Perspective,†IEEE International Conference on Solid State and Integrated Circuit Technology, January 2015.

      [11] Navneet Gupta et al, “3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power Applications,†Design, Automation and Test in Europe Conference and Exhibition, April 2016.

      [12] J Singh et al, “A Novel Si-Tunnel FET based SRAM design for Ultra Low Power 0.3 V Applications,†Asia and Pacific Design Automation Conference, February 2010.

      [13] Anurag Dandotiya and Amit S. Rajput, “SNM Analysis of 6T SRAM at 32nm and 45nm Technique,†International Journal of Computer Applications, Vol 98, No 7, July 2014.

      [14] K.Zhang et al, “SRAM Design on 65nm CMOS Technology with Integrated Leakage Reduction Scheme,†Symposium on VLSI Circuits, October 2004.

      [15] Qiang Tong et al, “A Low Power, High Speed FinFET based 6T SRAM cell with Enhanced write ability and read stability,†International SoC Design Conference, December 2016.

      [16] Jency Rubia et al, “Analysis, Design and Implementation of 4-bit Full Adder using FinFET,†Journal of Convergence Information Technology (JCIT), Vol 10, No 2, March 2015.

      [17] Jency Rubia and Babitha, “Design of Low power 4-bit ALU using 32nm FinFET Technology,†International Journal of Pure and Applied Mathematics, Vol 120, No 6, July 2018.

      [18] [18] Bibin Lawrence and Jency Rubia, “Review of FinFET Technology and Circuit Design Challenges,†International Journal of Engineering Research and Applications, Vol 5, No 12, December 2015.

      [19] Babitha and Jency, “Performance Investigation of a Full Adder using CNFET Technology,†International Conference on Engineering and Technology (ICET), December 2016.

      [20] Rajat Mahapatra et al, “High SNM 32nm CNFET based 6T SRAM cell design Considering Transistor Ratio,†International Conference on Electronics and Communication Systems, September 2014.

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  • How to Cite

    Rubia J, J., Lincy R, B., & ., . (2018). Investigation of 6T SRAM Characteristics Using TFET. International Journal of Engineering & Technology, 7(3.34), 980-983. https://doi.org/10.14419/ijet.v7i3.34.25344