Power Optimization in System Level Using Profiling Technique

  • Authors

    • Karthik. S
    • Balaji T.S
    • Nihitha S.S
    • K. Priyadarsini
    2018-10-02
    https://doi.org/10.14419/ijet.v7i4.10.26665
  • Profiling, Vivado, Xilinx SDK, Zynq, FPGA

  • Abstract

    Power optimization has become an essential and major source of concern at the system level design. With the shrink in transistor length and the attractiveness of handy electronic devices, power dissipation has become a serious issue. System level power optimization technique gains more popularity since many techniques can be applied in reduction of power. Although, there are numerous techniques to reduce power dissipation, simpler methods has not been implemented on a system level. In this paper we use profiling technique, a process which helps one to know which portion of the function takes more time compared to other during the simulation. The portion which takes large time for simulation is port mapped to the FPGA while the rest is assigned to the processor. By this technique we can see considerable amount of power savings.

     

     

     

  • References

    1. [1] Kaushik Roy , Mark C. Johnson, Software design for low power,Low power design in deep submicron electronics, Kluwer Academic Publishers, Norwell, MA, 1997.

      [2] Harris, E.P., Depp S.W., Pence W,E., Kirkpatrick S. et ai,"Technology directions for portable computers" Proceedings of the IEEE, 83(4), 636-657.

      [3] DeFreef E., Gatthoor F. Deman H. "Memory access coalescing:Atechnique for elimilating redundant memory access" ACM SIGPLAN Notices, 26(6).

      [4] John L. Hennessy, David A. Patterson. "Computer Architecture: A Quantitative Approach"3rd edition. Morgan Kaufmann. 2003.

      [5] Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, MasahiroFujita. "Power Analysis and MinimizationTechniques forEmbedded DSP Software", IEEE Trans. on Very Large Scale Integration Systems, Vol. 5, No. 1 , March 1997.

      [6] Qiaing Tong, Ken Choi, Jun Dong Cho, “A Review on System Level Low Power Techniquesâ€, IEEE Trans. On SOC Design conference, Nov 2014.

      [7] Karthik.S, Dr.S.Saravanakumar, “Parallel HDL Simulation Using Heterogeneous FPGA Architecturesâ€, International Journal of Applied Engineering Research, ISSN 0973-4562, Vol.10, No.20, 2015.

      [8] Lam, William K. “Hardware Design Verification: Simulation and Formal Method-Based Approacheâ€,. Prentice Hall, 2005

      [9] Karthik.S, Dr.S.Saravanakumar, “Comparative Study of Homogeneous and Heterogeneous Processor in FPGA For Functional Verification†International Journal of Applied Engineering Research, ISSN 0973-4562, Volume 10, No.17, 2015.

      [10] https://www.xilinx.com/support/documentaion/sw_manuals/edk10_est_rm.pdf

      [11] https://www.xilinx.com/publications/prod_mktg/vivado/Vivado_9_Reasons_Backgrounder

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  • How to Cite

    S, K., T.S, B., S.S, N., & Priyadarsini, K. (2018). Power Optimization in System Level Using Profiling Technique. International Journal of Engineering & Technology, 7(4.10), 1037-1040. https://doi.org/10.14419/ijet.v7i4.10.26665

    Received date: 2019-01-29

    Accepted date: 2019-01-29

    Published date: 2018-10-02