Performance of potential distribution of CSDG MOSFET using evanescent-mode analysis

  • Authors

    • Uchechukwu A.Maduagwu Department of Electronic Engineering, Howard College, University of KwaZulu-Natal, Durban - 4041
    • Viranjay M.Srivastava Department of Electronic Engineering, Howard College, University of KwaZulu-Natal, Durban - 4041
    2019-04-07
    https://doi.org/10.14419/ijet.v7i4.27201
  • CSDG MOSFET, 2D analysis, Potential Distribution, Microelectronics, Nanotechnology, VLSI.

  • Abstract

    In nanotechnology, to overcome the restriction on the scaling (sizing) of the MOSFET, a cylindrical structure of MOSFET is suitable. It increases the switching speed (at Radio Frequency level), current flow (Double traditional MOSFET), and packaging density (billions of transistors per unit area). In this research work, analytical 2D model for potential distribution of Cylindrical Surrounding Double-Gate (CSDG) MOSFET has been derived, based on 2D Poisson solution using Evanescent-Mode analysis. The impact of Short Channel Effects (SCEs) on the channel potential has been evaluated which is based on the device parameters such as channel length, drain to source bias voltage, silicon thickness, and oxide thickness. Also, the derived closed-form expressions surface potential for both the inner and outer gate of the CSDG MOSFET produced a relatively the same results. The accuracy has been validated through the simulation analysis.

     

     


     

  • References

    1. [1] G. Dambrine, C. Raynaud, Dimitri Lederer, Morin Dehan, O. Rozeaux, M. Vanmackelberg, et al., "What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?," IEEE Electron Device Letters, vol. 24, no. 3, pp. 189-191, 2003.

      [2] Surya Veeraraghavan and Jerry G Fossum, "Short-channel effects in SOI MOSFETs," IEEE Transactions on Electron Devices, vol. 36, no. 3, pp. 522-528, 1989. https://doi.org/10.1109/16.19963.

      [3] K. Konrad Young, "Short-channel effect in fully depleted SOI MOSFETs," IEEE Transactions on Electron Devices, vol. 36, no. 2, pp. 399-402, Feb. 1989. https://doi.org/10.1109/16.19942.

      [4] Kunihiro Suzuki, Yoshiharu Tosaka, and Toshihiro Sugii, "Analytical threshold voltage model for short channel double-gate SOI MOSFETs," IEEE Transactions on Electron Devices, vol. 43, no. 7, pp. 1166-1168, Jul. 1996. https://doi.org/10.1109/16.502429.

      [5] Don Monroe and J. M. Hergenrother, "Evanescent-mode analysis of short-channel effects in fully depleted SOI and related MOSFETs," in Proc. of IEEE International SOI Conference, 5-8 Oct. 1998, pp. 157-158.

      [6] Viranjay M. Srivastava, Kalyan S. Yadav, and Ghanashyam Singh, "Design and performance analysis of double-gate MOSFET over single-gate MOSFET for RF switch," Microelectronics Journal, vol. 42, no. 3, pp. 527-534, Oct. 2011. https://doi.org/10.1016/j.mejo.2010.12.007.

      [7] Antonioramon Lazaro, B. Nae, C. Muthupandian, and B. Iníguez, "High-frequency compact analytical noise model of gate-all-around MOSFETs," Semiconductor Science and Technology, vol. 25, no. 3, p. 035015, Feb. 2010. https://doi.org/10.1088/0268-1242/25/3/035015.

      [8] Qiang Chen, Bhavna Agrawal, and James D. Meindl, "A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs," IEEE Transactions on electron devices, vol. 49, no. 6, pp. 1086-1090, Aug. 2002. https://doi.org/10.1109/TED.2002.1003757.

      [9] Te Kuang Chiang, "A new quasi-2-D threshold voltage model for short-channel junctionless cylindrical surrounding gate (JLCSG) MOSFETs," IEEE Transactions on Electron Devices, vol. 59, no. 11, pp. 3127-3129, Sept. 2012. https://doi.org/10.1109/TED.2012.2212904.

      [10] Guangxi Hu, Ping Xiang, Zhihao Ding, Ran Liu, Lingli Wang, and Ting Ao Tang, "Analytical models for electric potential, threshold voltage, and subthreshold swing of junctionless surrounding-gate transistors," IEEE Transactions on Electron Devices, vol. 61, no. 3, pp. 688-695, Mar. 2014. https://doi.org/10.1109/TED.2013.2297378.

      [11] Guangxi Hu, Shuyan Hu, Jianhua Feng, Ran Liu, Lingli Wang, and Lirong Zheng, "Analytical models for channel potential, threshold voltage, and subthreshold swing of junctionless triple-gate FinFETs," Microelectronics Journal, vol. 50, pp. 60-65, Feb. 2016. https://doi.org/10.1016/j.mejo.2016.02.003.

      [12] Christopher P. Auth and James D. Plummer, "Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's," IEEE Electron Device Letters, vol. 18, no. 2, pp. 74-76, Feb. 1997. https://doi.org/10.1109/55.553049.

      [13] Sang Hyun Oh, Don Monroe, and J. M. Hergenrother, "Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs," IEEE electron device letters, vol. 21, no. 9, pp. 445-447, Sept. 2000. https://doi.org/10.1109/55.863106.

      [14] David J. Frank, Yuan Taur, and H. S. P. Wong, "Generalized scale length for two-dimensional effects in MOSFETs," IEEE Electron Device Letters, vol. 19, no. 10, pp. 385-387, Oct. 1998. https://doi.org/10.1109/55.720194.

      [15] Hossain M. Fahad, Casey E. Smith, Jhonathan P. Rojas, and Muhammad M. Hussain, "Silicon nanotube field effect transistor with core–shell gate stacks for enhanced high-performance operation and area scaling benefits," Nano letters, vol. 11, no. 10, pp. 4393-4399, Sept. 2011. https://doi.org/10.1021/nl202563s.

      [16] Viranjay M. Srivastava and Ghanshyam Singh, "MOSFET Technologies for Double-Pole Four-Throw Radio-Frequency Switch, 1st Ed, Springer, 2014. https://doi.org/10.1007/978-3-319-01165-3.

      [17] Yijian Chen and Weiling Kang, "Experimental study and modeling of double-surrounding-gate and cylindrical silicon-on-nothing MOSFETs," Microelectronic Engineering, vol. 97, pp. 138-143, 2012. https://doi.org/10.1016/j.mee.2012.05.009.

      [18] Hiroshi Iwai, "Roadmap for 22 nm and beyond," Microelectronic Engineering, vol. 86, no. 7-9, pp. 1520-1528, 2009. https://doi.org/10.1016/j.mee.2009.03.129.

      [19] Viranjay M. Srivastava, K. S. Yadav, and G. Singh, "Drain current and noise model of cylindrical surrounding double-gate MOSFET for RF switch," Procedia Engineering, vol. 38, pp. 517-521, Jun. 2012. https://doi.org/10.1016/j.proeng.2012.06.064.

      [20] Viranjay M. Srivastava, K. S. Yadav, and G. Singh, "Explicit model of cylindrical surrounding double-gate MOSFETs," WSEAS Trans. on Circuits and Systems, vol. 12, no. 3, pp. 81-90, Mar. 2013.

      [21] Viranjay M. Srivastava, "Effect of threshold voltage of cylindrical surrounding double-gate MOSFET for wireless sensors networks RF switches," in Proc. of World Congress on Engineering and Computer Science, San Francisco, USA, 22-24 Oct. 2014, pp. 6-10.

      [22] Jay H. K. Verma, Subhasis Haldar, R. S. Gupta, and Mridula Gupta, "Modelling and simulation of subthreshold behaviour of cylindrical surrounding double gate MOSFET for enhanced electrostatic integrity," Superlattices and Microstructures, vol. 88, pp. 354-364, Dec. 2015. https://doi.org/10.1016/j.spmi.2015.09.024.

      [23] Chuyang Hong, Jun Zhou, Jiasheng Huang, Rui Wang, Wenlong Bai, James B Kuo, et al., "A general and transformable model platform for emerging multi-gate MOSFETs," IEEE Electron Device Letters, vol. 38, no. 8, pp. 1015-1018, Jun. 2017. https://doi.org/10.1109/LED.2017.2722227.

      [24] Sourav Bairagya and Abhishek Chakraborty, "An analytical model for double surrounding gate MOSFET," in Devices for Integrated Circuit (DevIC), 2017, 23-24 Mar. 2017, pp. 721-725.

      [25] Yasuhisa Omura, Seiji Horiguchi, Michiharu Tabe, and Kenji Kishi, "Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs," IEEE Electron Device Letters, vol. 14, no. 12, pp. 569-571, Dec. 1993. https://doi.org/10.1109/55.260792.

      [26] Uchechukwu A. Maduagwu and Viranjay M. Srivastava, "Bridge rectifier with Cylindrical Surrounding Double-Gate MOSFET: A model for better efficiency," in Proc. of International Conference on Domestic Use of Energy (DUE), Cape Town, South Africa, 4-5 April 2017, pp. 109-113. https://doi.org/10.23919/DUE.2017.7931832.

      [27] Okikioluwa E. Oyedeji and Viranjay M. Srivastava, "Cylindrical surrounding double-gate MOSFET based amplifier: A circuit perspective," in Proc. of 2017 International Conference on Intelligent Computing, Instrumentation and Control Technologies (ICICICT), Kerala, India, 6-7 Jul. 2017, pp. 152-155. https://doi.org/10.1109/ICICICT1.2017.8342551.

      [28] Viranjay M. Srivastava, Kalyan S. Yadav, and Ghanashyam Singh, "Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch," Microelectronics Journal, vol. 42, no. 10, pp. 1124-1135, Oct. 2011. https://doi.org/10.1016/j.mejo.2011.07.003.

      [29] Uchechukwu A. Maduagwu and Viranjay M. Srivastava, "Analytical performance of the threshold voltage and subthreshold swing of CSDG MOSFET," Journal of Low Power Electronics, vol. 10, no. 1, pp. 1-20, 2019. https://doi.org/10.3390/jlpea9010010.

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  • How to Cite

    A.Maduagwu, U., & M.Srivastava, V. (2019). Performance of potential distribution of CSDG MOSFET using evanescent-mode analysis. International Journal of Engineering & Technology, 7(4), 5649-5653. https://doi.org/10.14419/ijet.v7i4.27201

    Received date: 2019-02-11

    Accepted date: 2019-03-10

    Published date: 2019-04-07