Dynamic Threshold MOSFET for Low Power VLSI Circuit Design

Abstract

In this abstract, we investigate a noble low power VLSI logic design technique by applied substrate bias to MOSFET & control threshold voltage (VTH) of MOSFET device  i.e. dynamic threshold MOS (DTMOS) logic design for combinational digital logic gates. DTCMOS logic design has larger driving ability with low leakage current ( i.e. low power dissipation) as compare to  ratio-less static CMOS logic design. DTMOS approach that takes advantage of partially-depleted SOI technology, by providing an fitting substrate bias that varies according to gate voltage(VG), As we know that  the VTH of the device is depending on its VG (i.e.by vary gate voltage we control the VTH of MOSFET). Under above circumstances, an improvement in delay while using less power than conventional transistors can be achieved. The behavioural comparison of DTMOS & CMOS logic design circuit are funded with respect to parameters such as Power dissipation, Propagation delay & Figure of merit evaluated through circuit simulator CAD tool HSPICE.