Implementation of Phase Locked Loop for FM Demodulator Circuit

  • Authors

    • Alpana Amit Deshmukh SGSITS,Indore,India
    • Radheshyam Gamad SGSITS,Indore,India
    • Deepak Kumar Mishra SGSITS,Indore,India
    2019-06-30
    https://doi.org/10.14419/ijet.v7i4.28025
  • Phase Locked Loop, Fast Fourier Transform, Voltage Controlled Oscillator, Frequency Modulation, Intermediate Frequency

  • Abstract

    This paper aims to implement the phase locked loop for the FM demodulator circuit in Intermediate frequency band. Implementation of the proposed design is done using Simulink; further simulation is presented using Matlab as well as a comparative analysis of VCO parameters using charge pump, linearized and baseband are discussed. Charge pump based PLL design achieved phase noise of -120 dBc/Hz at 10 MHz offset frequency. Paper also presented FM demodulated output for 5000 kHz sampling frequency and 2000 KHz carrier frequency at 50 Hz deviation frequency. Simulation results are reported in tabular and graphical form.

     

     

  • References

    1. [1] N. Haque, P. K. Boruah and T. Bezboruah, IAENG Member, “Modeling and Simulation of Second-order Phase-locked Loop for Studying the Transient Behavior during Frequency Acquisition and Trackingâ€, Proceedings of the World Congress on Engineering 2010 Vol II WCE 2010, June 30 - July 2, 2010, London, U.K.

      [2] Rui He, Jun Li, Woogeun Rhee, and Zhihua Wang, “Transient Analysis of Nonlinear Settling Behavior in Charge-Pump Phase-Locked Loop Designâ€, pp. 469-3472, 2009.

      [3] A. Telba, “Modeling and Simulation of Wideband Low Jitter Frequency Synthesizerâ€, 2009 IEEEProceedings of the World Congress on Engineering 2010 Vol II, pp. 317-319, June 30 July 2, 2010, London, U.K.

      [4] Behzad Razavi, “Design of Analog CMOS Integrated Circuits, Xi'an Jiaotong University Pressâ€, pp. 482-576, 2002.

      [5] H. Ahn and D. All stotâ€, “A Low-Jitter 1.9-V CMOS PLL for Ultra SPARC microprocessor applicationsâ€, IEEE J. Solid-State Circuits, vol. 35, pp. 450–454, March- 2000.

      [6] B.K. Mishra, Sandhya Save, Swapna Patil, “Design and Analysis of Second and Third Order PLL at 450MHzâ€, International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, pp. 97-114, March- 2011.

      [7] Johannes Jacobus Grobbelaar, “Phase Noise Measurementâ€, thesis submitted in Stellenbosch University, 2011.

      [8] Umakanta Nanda, Jyotirmayee Sarangi, Prakash Kumar Rout, “Study of Recent Charge Pump Circuits in Phase-Locked Loopâ€, I.J. Modern Education and Computer Science, pp. 59-65, 2016.

      [9] Alpana A. Deshmukh, R. S. Gamad, D. K. Mishra, “Modeling and Simulation of Hilbert Transform Phase Detector Based on All Digital Phase-Locked Loopâ€, International Journal of Electronics Engineering, Vol.10 Issue 2 pp. 648-664 June 2018, Dec- 2018.

      [10] Robert C. Chang and lung-Chih Kuo, “A New Low-Voltage Charge Pump Circuit for PLLâ€, IEEE International Symposium on Circuits and Systems, Geneva, Switzerland, pp. 701-704, May- 2000.

      [11] Pavan Kumar Hanumolu, Merrick Brownlee, Kartikeya Mayaram, and Un-Ku Moon, "Analysis of Charge-Pump Phase-Locked Loopsâ€, IEEE Transactions On Circuits And Systems—I: Regular Papers, Vol. 51, No. 9, pp. 1665-1674, September- 2004.

      [12] H. Rategh, H. Samavati, and T. Lee, "A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver," IEEE J. Solid-State Circuits, vol. 35, pp. 780–787, May- 2000.

      [13] M. Meghelli, B. Parker, H. Ainspan, and M. Soyuer, “SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems,†IEEE J. Solid-State Circuits, vol. 35, pp. 1992–1995, Dec- 2000.

      [14] M. Perrott, “Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits,†in Proc. Design Automation Conf., pp. 498–503, June- 2002.

      [15] Rui He, Jun Li, Woogeun Rhee, and Zhihua Wang, “Transient Analysis of Nonlinear Settling Behavior in Charge-Pump Phase-Locked Loop Designâ€, pp. 469-3472, 2009.

      [16] Sun, Ray. "How to Design and Debug a Phase-Locked Loop (PLL) Circuit."

      [17] Praveen Kumar, “Digital Phase Locked Loopâ€, IETE Journal of Electronics, Vol. 52, issue 1, pp. 5-10, September-2014.

      [18] “Phillip E. Allen Ece 6440- Frequency Synthesizers†pp. 080-2-080 -6.

      [19] X. Deng, J. Yang and J. Wu, “Jitter and Phase Noise of ADPLL Due To PSN With Deterministic Frequencyâ€, International Journal of Electronics, Taylor and Francis, Vol. 98, No. 9, pp. 1259–1268, September 2011.

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  • How to Cite

    Amit Deshmukh, A., Gamad, R., & Kumar Mishra, D. (2019). Implementation of Phase Locked Loop for FM Demodulator Circuit. International Journal of Engineering & Technology, 7(4), 6519-6522. https://doi.org/10.14419/ijet.v7i4.28025

    Received date: 2019-02-27

    Accepted date: 2019-06-12

    Published date: 2019-06-30