Design of Dual Stage 180nm CMOS High Gain Low Noise Amplifier for 5G Applications

  • Authors

    • Anjana Jyothi Banu
    • Dr. G.Kavya
    • D. Jahnavi
    https://doi.org/10.14419/ijet.v7i4.6.28932
  • ADS, CMOS, Low noise amplifier, Noise canceling, 5G

  • Abstract

    Low noise amplifier (LNA) is an important block in receiver front-end as it is used to amplify the weak signals from the antenna. This paper presents a design of low noise amplifier for 5G applications based on 180nm CMOS technology. LNA is designed to operate at 26 GHz in the K-band. The proposed circuit is a two stage LNA composing of a common-source followed by a Cascode stage. To minimize the noise figure (NF), the common-source (CS) structure along with the noise cancellation technique is employed in the first stage. The Cascode structure is used in the second stage to enhance the power gain and provide better reverse isolation. The measurement result depicts that a gain of 17.105 dB and noise figure of 1.016 dB at 26 GHz is obtained. The input and output impedance matching have been performed to achieve S11 of -19.185 dB and S22 of -38.884 dB. The circuit is designed and simulated using Advanced design system (ADS) software.

     

  • References

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  • How to Cite

    Jyothi Banu, A., G.Kavya, D., & Jahnavi, D. (2018). Design of Dual Stage 180nm CMOS High Gain Low Noise Amplifier for 5G Applications. International Journal of Engineering & Technology, 7(4.6), 573-576. https://doi.org/10.14419/ijet.v7i4.6.28932

    Received date: 2019-04-22

    Accepted date: 2019-04-22