Investigation on Low Power for Reducing Counter Delay Digital Circuit Using 45nm Technology

  • Authors

    • Mr. S.Mohamed Sulaiman
    • Dr. B.Jaison
    • Dr. M.Anto Bennet
    • S. Purushoth
    • R. Jawahar
    • T. Suriya
    https://doi.org/10.14419/ijet.v7i4.6.29035
  • .

  • Abstract

    The counter circuit is a basic component in floating point operation. The main aim is to speed up the operation of the circuit. The new derived Boolean function which is designed by the concept of transmission gate logic in order to reduce the number of gates and speed the circuit operation. By the transmission gate logic the 8 bit counter circuit is designed. Moreover, 16 bit and 32 bit circuit is designed using 45 nm technology. The result of 16 and 32bit circuits are better than the reported design and by comparison, proposed design is faster and the delay of the circuit is minimized when compared to the reported design.

  • References

    1. [1] J. Miao and S. Li, "A design for high speed leading-zero counter," 2017 IEEE International Symposium on Consumer Electronics (ISCE), Kuala Lumpur, 2017, pp. 22-23.doi: 10.1109/ISCE.2017.8355536.

      [2] H. Reyserhove and W. Dehaene, "A Differential Transmission Gate Design Flow for Minimum Energy Sub-10-pJ/Cycle ARM Cortex-M0 MCUs," in IEEE Journal of Solid-State Circuits, vol. 52, no. 7, pp. 1904-1914, July 2017.doi: 10.1109/JSSC.2017.2693241.

      [3] S. Kumar, A. Kumar and P. Bansal, "High speed area efficient 1-bit hybrid full adder,"2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), Chennai, 2016, pp. 682-686.
      doi: 10.1109/ICEEOT.2016.7754768.

      [4] H. Reyserhove and W. Dehaene, "A 16.07pJ/cycle 31MHz fully differential transmission gate logic ARM Cortex M0 core in 40nm CMOS,"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne,2016,pp.257-26.doi: 0.1109/ESSCIRC.2016.7598291.

      [5] Dr. AntoBennet, M, Sankar Babu G, Suresh R, Mohammed Sulaiman S, Sheriff M, Janakiraman G ,Natarajan S, “Design & Testing of Tcam Faults Using TH Algorithmâ€, Middle-East Journal of Scientific Research 23(08): 1921-1929, August 2015 .

      [6] Dr. AntoBennet, M “Power Optimization Techniques for sequential elements using pulse triggered flipflopsâ€, International Journal of Computer & Modern Technology , Issue 01 ,Volume01 ,pp 29-40, June 2015.

      [7] Dr. AntoBennet, M,Manimaraboopathy M,P. Maragathavalli P,Dinesh Kumar T R, “Low Complexity Multiplier For Gf(2m) Based All One Polynomialâ€, Middle-East Journal of Scientific Research 21 (11): 2064-2071, October 2014.

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  • How to Cite

    S.Mohamed Sulaiman, M., B.Jaison, D., M.Anto Bennet, D., Purushoth, S., Jawahar, R., & Suriya, T. (2018). Investigation on Low Power for Reducing Counter Delay Digital Circuit Using 45nm Technology. International Journal of Engineering & Technology, 7(4.6), 583-585. https://doi.org/10.14419/ijet.v7i4.6.29035

    Received date: 2019-04-27

    Accepted date: 2019-04-27