FPGA Realization of Deep Neural Network for Hardware Trojan Detection

  • Authors

    • Varun Reddy Amrita Vishwa Vidhyapeetham
    • Nirmala Devi M Amrita Vishwa Vidhyapeetham
    2020-08-30
    https://doi.org/10.14419/ijet.v9i3.30946
  • Deep Neural Network, Deep Learning, FPGA, Hardware Trojan, Random forest classifier

  • Abstract

    With the increase in outsourcing design and fabrication, malicious third-party vendors often insert hardware Trojan (HT) in the integrated Circuits(IC). It is difficult to identify these Trojans since the nature and characteristics of each Trojan differ significantly. Any method developed for HT detection is limited by its capacity on dealing with varied types of Trojans. The main purpose of this study is to show using deep learning (DL), this problem can be dealt with some extent and the effect of deep neural network (DNN) when it is realized on field programmable gate array (FPGA). In this paper, we propose a comparison of accuracy in finding faults on ISCAS’85 benchmark circuits between random forest classifier and DNN. Further for the faster processing time and less power consumption, the network is implemented on FPGA. The results show the performance of deep neural network gets better when a large number of nets are used and faster in the execution of the algorithm. Also, the speedup of the neuron is 100x times better when implemented on FPGA with 15.32% of resource utilization and provides less power consumption than GPU.

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  • How to Cite

    Reddy, V., & M, N. D. (2020). FPGA Realization of Deep Neural Network for Hardware Trojan Detection. International Journal of Engineering & Technology, 9(3), 764-769. https://doi.org/10.14419/ijet.v9i3.30946

    Received date: 2020-07-03

    Accepted date: 2020-08-23

    Published date: 2020-08-30