FPGA implementation of RS codec with interleaver in DVB-T using VHDL

  • Authors

    • Sara Kamar Modern Academy for Engineering and Technology
    • Abdelmoniem Fouda Modern Academy for Engineering and Technology
    • Abdelhalim Zekry Ain Shams Universty
    • Abdelmoniem Elmahdy Modern Academy for Engineering and Technology
    2017-11-28
    https://doi.org/10.14419/ijet.v6i4.8205
  • Convolutional interleaver/Deinterleaver, DVB-T, Outer Coding, RS (204, 188), VHDL.

  • Abstract

    Digital television (DTV) provides a huge amount of information to many users at low cost. Recently, it can be packaged and fully integrated into completely digital transmission networks. Reed-Solomon code (RS) is one type of error correcting codes that can be used to enhance the performance of DTV. Interleaving/deinterleaving process enhances the performance of channel errors by spreading out random errors, very high-speed hardware description language (VHDL) is used in electronic design automation. It can be used as a general-purpose parallel programming language.

    This paper presents VHDL program for Reed-Solomoncodec (204, 188) and convolutional interleaver/deinterleaver, used in Digital Video Broadcasting-terrestrial system (DVB-T), according to ETSI EN 300 744 V1.5.1 standard. The VHDL programs are implemented on Xilinx 12.3 ISE and then simulated and tested via ISE simulator then the code is synthesized on FPGA device the results are compared with IP core for Xilinx 12.3 ISE, which gives the same results.

  • References

    1. [1] O'leary, S. (2000). Understanding digital terrestrial broadcasting. (p. 1:14) London, Boston: Artech House.

      [2] Sandeep Kaurs “VHDL implementation of Reed – Solomon codes†Thesis of master of Engineering in electronics and communication engineering, Thapar institute of engineering & technology, Deemed university, PatialaA – 147004, 2006.

      [3] Priyanka Dayal, R. K. (2014). "Implementation of Reed-Solomon codec for IEEE 802.16 network using VHDL code". (p. 452:455). India: International Conference on Reliability, Optimization and Information Technology.

      [4] Bhawna Tiwari, RajeshMehra, “FPGAImplementation of RS Codec (Dayal, "Implementation of Reed Solomon CODEC for IEEE 802.16 network using VHDL code, 2014)for Digital Video Broadcastingâ€, VSRD-IJEECE Journal,Vol. 2 (2), 68-77, 2012.

      [5] Lamia, M.Fouraty, “A reconfigurable FEC system based on Reed Solomon codec for DVB and 802.16 network†Electronic and information technology laboratory (L.E.T.I), Sfax national engineering school, 3038 Sfax Tunis.

      [6] Sklar, B., Digital Communications: Fundamentals and Applications, (p 437:468) Second Edition (Upper Saddle River, NJ) Prentice-Hall, 2001).

      [7] Haoyi Zhang “Reed-Solomon code (204, 188) encoder/decoder design, synthesis and simulation with QUARTUS â…±â€A graduate project submitted in partial fulfillment of the requirements For the degree of Master of Science in Electrical Engineering, December, 2013.

      [8] L.H. Charles Lee “Error control block codes for communication engineerâ€. (p. 120:163) London, Boston, Artech House

      [9] Aqib. Al Azad, Minhazul. Huq, Iqbalur, Rahman Rokon, “Efficient Hardware Implementation of Reed Solomon Encoder and Decoder in FPGA using Verilogâ€, International Conference on Advancements in Electronics and Power Engineering (ICAEPE'2011), Dec., 2011.

      [10] R.T. Chien, Cyclic Decoding Procedures for Bose-Chaudhuri-Hocquenghem Codes, IEEE Transactions on Information Theory, Vol. 10, No. 10, 357-363, 1964. https://doi.org/10.1109/TIT.1964.1053699.

      [11] Shu. Lin., Danial J. Costello, Jr. “Error control coding: Fundamental and application†(p.151:174), Prentce- Hall, Inc. Engelwood Cliffs, New Jersey 07632.

      [12] G.D. Forney, Generalized Minimum Distance Decoding, IEEE Transactions on Information Theory, Vol. IT- 12, No. 2, 125-131.

      [13] G.D. Forney, On Decoding BCH Codes, IEEE Transactions on Information Theory, 549-557.

      [14] ETSI EN300744“DigitalVideoBroadcasting (DVB); Framing structure, channel coding and modulation for digital terrestrial televisionâ€. Final draft, V1.5.1 (2004-06), 1-64.

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  • How to Cite

    Kamar, S., Fouda, A., Zekry, A., & Elmahdy, A. (2017). FPGA implementation of RS codec with interleaver in DVB-T using VHDL. International Journal of Engineering & Technology, 6(4), 171-180. https://doi.org/10.14419/ijet.v6i4.8205

    Received date: 2017-08-08

    Accepted date: 2017-11-22

    Published date: 2017-11-28