Ultra low power design approach of asynchronous delta sigma modulator

 
 
 
  • Abstract
  • Keywords
  • References
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  • Abstract


    Asynchronous Delta Sigma Modulator (ADSM) is assuming an extremely vital part in the majority of conveying device  and information convertor and in this manner requires the exceptional consideration in outlining. The execution of the vast majority of the device having DSM as an essential segment is described by the execution of the DSM hardware. This paper introduces the audit of work performed in planning of Asynchronous Delta Sigma Modulator. Latest trends are about the utilization of ADSM for various applications. Contrasting the execution of various ADSM circuits, an execution paradigm is settled for ADSM plan. The execution criteria basically think about the Low working voltages, low power utilization, high SNDR and better focus recurrence. At that point a strategy is suggested that characterizes the High execution ADSM that influence joined utilization of various methods to like inverse operation and mass driven MOS for ultra low power outline and enhancing the execution of an Asynchronous Delta Sigma Modulator.


  • Keywords


    Asynchronous Delta Sigma Modulator (ADSM),Ultra Low Power Design, Centre Frequency, PSD.

  • References


      [1] Roza E, “Analog-to-digital conversion via duty-cycle modulation”, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, Vol.44, No.11, (1997), pp.907–914.

      [2] Daniels J, Dehaene W, Steyaert MSJ & Wiesbauer A, “A/D conversion using asynchronous delta–sigma modulation and time-to-digital conversion”, IEEE Trans. Circuits Syst. I, Reg. Papers, Vol.57, No.9, (2010), pp.2404–2412.

      [3] Matic T, Svedek T & Herceg M, “A method for the Schmitt-trigger propagation-delay compensation in asynchronous sigma–delta modulator”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.59, No.7, (2012), pp.404-408.

      [4] Ferreira LH & Sonkusale SR, “A 60-dB gain OTA operating at 0.25-V power supply in 130-nm digital CMOS process”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.61, No.6, (2014), pp.1609-1617.

      [5] Manju, K., Sabeenian, R.S., Surendar, A.”A review on optic disc and cup segmentation”,(2017) Biomedical and Pharmacology Journal, 10 (1), pp. 373-379.

      [6] Surendar, A., Rani, N.U.”High speed data searching algorithms for DNA searching”,(2016) International Journal of Pharma and Bio Sciences, 2016 (Special Issue), pp. 73-77.

      [7] Surendar, A., Arun, M.”Efficient DNA sequence analysis for reduced gene selection using frequency analysis”, (2016) Journal of Chemical and Pharmaceutical Sciences, 9 (4), pp. 3367-3373.

      [8] Surendar, A., George, A.”A real-time searching and sequencing assembly platform based on an FPGA implementation for Bioinformatics applications”,(2016) International Journal of Pharma and Bio Sciences, 7 (4), pp. B642-B647.

      [9] Daniels J, Dehaene W, Steyaert MS & Wiesbauer A, “A/D conversion using asynchronous delta-sigma modulation and time-to-digital conversion”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.57, No.9, (2010), pp.2404-2412.

      [10] Chakraborty S, Mallik A, Sarkar CK & Rao VR, “Impact of halo doping on the subthreshold performance of deep submicrometer CMOS devices and circuits for ultralow power analog/mixed-signal applications”, IEEE Trans. Electron Devices, Vol.54, No.2, (2007), pp.241–248.

      [11] Aziz PM, Sorensen HV & Vn der Spiegel J, “An overview of sigma-delta converters”, IEEE signal processing magazine, Vol.13, No.1, (1996), pp.61-84.

      [12] Ouzounov S, Roza E, Hegt H, van der Weide G & van Roermund A, “An 8MHz, 72 Db SFDR Asynchronous Sigma-Delta Modulator with 1.5mW Power Dissipation”, Symposium On VLSl Circuits Digest of Technical Papers, (2004).


 

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Article ID: 8929
 
DOI: 10.14419/ijet.v7i1.1.8929




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