Implementation of FPGA based MRPMA for high performance applications

  • Authors

    • T. Siva Sankara Phani
    • M. Sujatha
    • K. Hari Kishore
    • M. Durga Prakash
    2017-12-31
    https://doi.org/10.14419/ijet.v7i1.5.9139
  • FFT, DCT, FIR, Channel encoder, FPGA, MRPMA, NoC.

  • Abstract

    In the last few decay, Network on Chip’s (NoC) are the powerful chips for high speed communications pertaining to 802.11 Ethernet protocol which is a need to be reconfigurable for successful data frame transmission. The existing architectures like coarse grained reconfigurable, ALU cluster and expression grain reconfigurable architecture and look-up-table used in fine grained reconfigurable devices requires a lot of storage memory, hardware resources such as slices, cell area and cell delay. To tackle these issues, Multigrained Reconfiguration and Parallel Mapping Architecture (MRPMA) is proposed and their performance analysis parameters are calculated. The MRPMA uses the four contributions to optimize Processing Elements (PE’s) operations: 1) Fast Fourier Transformation (FFT) to perform fixed point numbers to the configuration words, 2) Discrete Cosine Transformation (DCT) to analyze the data in the frequency domain, 3) Finite Impulse Response (FIR) for parallel mapping the data and 4) Channel encoder and decoder to encode the data and to calculate the shortest route from source to destination switch.   

  • References

    1. [1] G. Ansaloni, P. Bonzini, and L. Pozzi, “Design and architectural exploration of expression-grained reconfigurable arrays,†in Proc.6th Symp. Appl. Specific Process., Anaheim, CA, Jun. 2008, pp. 26–33.

      [2] Shouyi Yin, Xinhan Lin, Leibo Liu, Shaojun Wei, "Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures", IEEE Transactions on Parallel & Distributed Systems, vol. 27, no. , pp. 3199-3213, Nov. 2016.

      [3] R. Hartenstein, H. Grünbacher (Editors): The Roadmap to Reconfigurable computing Proc.FPL2000, Aug. 27-30,2000; LNCS, Springer-Verlag 2000

      [4] A dynamically reconfigurable system-on-a-chip architecture for future mobile digital signal processing (1999) by Ahmad Alsolaim , Jürgen Becker European signal processing conference.

      1. Bindra. Reconfigurable architectures chart a new course for DSPs. Electronic Design, pages 46–52, August 5 2002.

      [5] R. Hartenstein. A decade of reconfigurable computing: A visionary retrospective. In Proc. DATE, pages 642–649, 2001.

      [6] K. Compton, Architecture Generation of Customized Reconfigurable Hardware, Ph.D. Thesis, Northwestern University, Dept. of ECE, 2003.

      [7] B. Mei, S. Vernalde, D. Verkest, H. De Man, and R. Lauwereins, “ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix,†in Field Programmable Logic and Application. Berlin, Germany: Springer-Verlag, 2003, pp. 61–70.

      [8] F. Bouwens, M. Berekovic, B. De Sutter, and G. Gaydadjiev, “Architecture enhancements for the ADRES coarse-grained reconfigurable array,†in High Performance Embedded Architectures and Compilers. Berlin, Germany: Springer-Verlag, 2008, pp. 66–81.

      [9] Ricardo Ferreira. Et.al, “An FPGA-based Heterogeneous Coarse-Grained Dynamically Reconfigurable Architectureâ€, CASES’11, October 9–14, 2011, Taipei, Taiwan. Pp195-204, 2011 ACM 978-1-4503-0713-0/11/10

      [10] Shuang Liang.et.al, “A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Accelerationâ€, 10.1109/LCA.2015.2458318, IEEE Computer Architecture Letters, 1556-6056 (c) 2015 IEEE

      [11] Vuk Vranjkovi.et.al, “Coarse-grained Reconfigurable Hardware Accelerator of Machine Learning Classifiersâ€, IWEEIP 2016, 978-1-4673-9555-7/16, IEEE-2016.

      [12] Amit Kulkarni.et.al, “A fully parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applicationsâ€, 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 978-1-5090-3682-0/16, 10.1109/IPDPSW.2016.13

      [13] Dr. Seetaiah Kilaru, Hari Kishore K, Sravani T, Anvesh Chowdary L, Balaji T “Review and Analysis of Promising Technologies with Respect to fifth Generation Networksâ€, 2014 First International Conference on Networks & Soft Computing, ISSN:978-1-4799-3486-7/14,pp.270-273,August2014.

      [14] Meka Bharadwaj, Hari Kishore "Enhanced Launch-Off-Capture Testing Using BIST Designs†Journal of Engineering and Applied Sciences, ISSN No: 1816-949X, Vol No.12, Issue No.3, page: 636-643, April 2017.

      [15] N Bala Dastagiri, Kakarla Hari Kishore "Reduction of Kickback Noise in Latched Comparators for Cardiac IMDs†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.43, Page: 1-6, November 2016.

      [16] A Murali, K Hari Kishore, D Venkat Reddy "Integrating FPGAs with Trigger Circuitry Core System Insertions for Observability in Debugging Process†Journal of Engineering and Applied Sciences, ISSN No: 1816-949X, Vol No.11, Issue No.12, page: 2643-2650, December 2016.

      [17] Mahesh Mudavath, K Hari Kishore "Design of CMOS RF Front-End of Low Noise Amplifier for LTE System Applications Integrating FPGAs†Asian Journal of Information Technology, ISSN No: 1682-3915, Vol No.15, Issue No.20, page: 4040-4047, December 2016.

      [18] P Bala Gopal, K Hari Kishore, B.Praveen Kittu “An FPGA Implementation of On Chip UART Testing with BIST Techniquesâ€, International Journal of Applied Engineering Research, ISSN 0973-4562, Volume 10, Number 14 , pp. 34047-34051, August 2015

      [19] S Nazeer Hussain, K Hari Kishore "Computational Optimization of Placement and Routing using Genetic Algorithm†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.47, page: 1-4, December 2016.

      [20] N Bala Gopal, K Hari Kishore "Analysis of Low Power Low Kickback Noise in Dynamic Comparators in Pacemakers†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.44, page: 1-4, November 2016.

      [21] S.V.Manikanthan and V.Rama“Optimal Performance Of Key Predistribution Protocol In Wireless Sensor Networks†International Innovative Research Journal of Engineering and Technology ,ISSN NO: 2456-1983,Vol-2,Issue –Special –March 2017.

      [22] S.V.Manikanthan and T.Padmapriya “Recent Trends In M2m Communications In 4g Networks And Evolution Towards 5gâ€, International Journal of Pure and Applied Mathematics, ISSN NO:1314-3395, Vol-115, Issue -8, Sep 2017.

      [23] Rajesh, M., and J. M. Gnanasekar. "CONGESTION CONTROL USING AODV PROTOCOL SCHEME FOR WIRELESS AD-HOC NETWORK." Advances in Computer Science and Engineering 16.1/2 (2016): 19.

      [24] SHUBHANSHU GUPTA, S. KOLANGIAMMAL, T.PADMAPRIYA, “Smart Curtain Using Internet Of Things†International Innovative Research Journal of Engineering and Technology, Vol. 2, Special Issue, pp. 4-8.

  • Downloads

  • How to Cite

    Sankara Phani, T. S., Sujatha, M., Hari Kishore, K., & Durga Prakash, M. (2017). Implementation of FPGA based MRPMA for high performance applications. International Journal of Engineering & Technology, 7(1.5), 158-163. https://doi.org/10.14419/ijet.v7i1.5.9139

    Received date: 2018-01-11

    Accepted date: 2018-01-11

    Published date: 2017-12-31