VLSI design for efficient RSD-Based ECC processor using Karatsuba algorithm

  • Authors

    • Pasluri Bindu Swetha
    • V.J. Kishore Sonti
    • A. Murali
    2017-12-31
    https://doi.org/10.14419/ijet.v7i1.5.9140
  • Application Specific Instruction-set Processor (ASIP), Elliptic Curve Cryptography (ECC), Field Programmable Gate Array (FPGA), Karatsuba–Ofman Multiplication, Redundant Signed Digit (RSD).
  • In this paper, an exportable application-particular direction set elliptic bend cryptography processor in view of repetitive marked digit portrayal is proposed. The processor utilizes broad pipelining strategies for Karatsuba– Of man strategy to accomplish high throughput augmentation. Moreover, an effective particular viper without correlation and a high throughput measured divider, which brings about a short data path for expanded recurrence, are actualized. The proposed design of this paper investigation the rationale size, region and power utilization utilizing Xilinx 13.2. The expansion for the task is Vedic Sutra – Nikhilam Sutra.

  • References

    1. [1] S.-C. Chung, J.-W. Lee, H.-C. Chang, and C.-Y. Lee, “A highperformance elliptic curve cryptographic processor over GF(p) with SPA resistance,†in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2012, pp. 1456–1459.

      [2] J.-Y. Lai and C.-T. Huang, “Elixir: High-throughput cost-effective dualfield processors and the design framework for elliptic curve cryptography,†IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 11, pp. 1567–1580, Nov. 2008.

      [3] D. Karakoyunlu, F. K. Gurkaynak, B. Sunar, and Y. Leblebici, “Efficient and side-channel-aware implementations of elliptic curve cryptosystems over prime fields,†IET Inf. Secur., vol. 4, no. 1, pp. 30–43, Mar. 2010.

      [4] D. M. Schinianakis, A. P. Fournaris, H. E. Michail, A. P. Kakarountas, and T. Stouraitis, “An RNS implementation of an Fp elliptic curve point multiplier,†IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 6, pp. 1202–1213, Jun. 2009.

      [5] D. Schinianakis and T. Stouraitis, “Multifunction residue architectures for cryptography,†IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 4, pp. 1156–1169, Apr. 2014.

      [6] J. Vliegen et al., “A compact FPGA-based architecture for elliptic curve cryptography over prime fields,†in Proc. 21st IEEE Int. Conf. Appl.-Specific Syst. Archit. Process. (ASAP), Jul. 2010, pp. 313–316.

      [7] T. Güneysu and C. Paar, “Ultra high performance ECC over NIST primes on commercial FPGAs,†in Proc. 10th Int. Workshop Cryptograph. Hardw. Embedded Syst. (CHES), 2008, pp. 62–78.

      [8] P. L. Montgomery, “Modular multiplication without trial division,†Math. Comput., vol. 44, no. 170, pp. 519–521, Apr. 1985.

      [9] K. Sakiyama, N. Mentens, L. Batina, B. Preneel, and I. Verbauwhede, “Reconfigurable modular arithmetic logic unit for high-performance public-key cryptosystems,†in Proc. 2nd Int. Workshop Reconfigurable Comput., Archit. Appl., vol. 3985. 2006, pp. 347–357.

      [10] Byrne, E. Popovici, and W. P. Marnane, “Versatile processor for GF(pm) arithmetic for use in cryptographic applications,†IET Comput. Digit. Tech., vol. 2, no. 4, pp. 253–264, Jul. 2008.

      [11] J. Solinas, “Generalized Mersanne number,†Univ. Waterloo, Waterloo, ON, Canada, Tech. Rep. CORR 99-39, 1999.

      [12] S. Mane, L. Judge, and P. Schaumont, “An integrated prime-field ECDLP hardware accelerator with high-performance modular arithmetic units,†in Proc. Int. Conf. Reconfigurable Comput. FPGAs, Nov./Dec. 2011, pp. 198–203.

      [13] B. Ansari and M. A. Hasan, “High-performance architecture of elliptic curve scalar multiplication,†IEEE Trans. Comput., vol. 57, no. 11, pp. 1443–1453, Nov. 2008.

      [14] N. Smyth, M. McLoone, and J. V. McCanny, “An adaptable and scalable asymmetric cryptographic processor,†in Proc. Int. Conf. Appl.-Specific Syst., Archit. Processors (ASAP), Sep. 2006, pp. 341–346.

      [15] C. J. McIvor, M. McLoone, and J. V. McCanny, “Hardware elliptic curve cryptographic processor over GF(p),†IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 9, pp. 1946–1957, Sep. 2006.

      [16] K. Ananyi, H. Alrimeih, and D. Rakhmatov, “Flexible hardware processor for elliptic curve cryptography over NIST prime fields,†IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 8, pp. 1099–1112, Aug. 2009.

      [17] M. Hamilton and W. P. Marnane, “FPGA implementation of an elliptic curve processor using the GLV method,†in Proc. Int. Conf. Reconfigurable Comput. FPGAs (ReConFig), Dec. 2009, pp. 249–254.

      [18] Karatsuba and Y. Ofman, “Multiplication of multidigit numbers on automata,†Soviet Phys. Doklady, vol. 7, p. 595, Jan. 1963.

      [19] Avizienis, “Signed-digit numbe representations for fast parallel arithmetic,†IRE Trans. Electron. Comput., vol. EC-10, no. 3, pp. 389–400, Sep. 1961.

      [20] NIST. (2000). Recommended Elliptic Curves for Federal Government Use. [Online]. Available: http://csrc.nist.gov/encryption.

      [21] S. Yazaki and K. Abe, “VLSI design of Karatsuba integer multipliers and its evaluation,†Electron. Commun. Jpn., vol. 92, no. 4, pp. 9–20, 2009.

      [22] â€An Efficient Multiplication Algorithm Using Nikhilam Method†Shri Prakash Dwivedi.

      [23] Dr. Seetaiah Kilaru, Hari Kishore K, Sravani T, Anvesh Chowdary L, Balaji T “Review and Analysis of Promising Technologies with Respect to fifth Generation Networksâ€, 2014 First International Conference on Networks & Soft Computing, ISSN:978-1-4799-3486-7/14,pp.270-273,August2014.

      [24] Meka Bharadwaj, Hari Kishore "Enhanced Launch-Off-Capture Testing Using BIST Designs†Journal of Engineering and Applied Sciences, ISSN No: 1816-949X, Vol No.12, Issue No.3, page: 636-643, April 2017.

      [25] N Bala Dastagiri, Kakarla Hari Kishore "Reduction of Kickback Noise in Latched Comparators for Cardiac IMDs†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.43, Page: 1-6, November 2016.

      [26] A Murali, K Hari Kishore, D Venkat Reddy "Integrating FPGAs with Trigger Circuitry Core System Insertions for Observability in Debugging Process†Journal of Engineering and Applied Sciences, ISSN No: 1816-949X, Vol No.11, Issue No.12, page: 2643-2650, December 2016.

      [27] Mahesh Mudavath, K Hari Kishore "Design of CMOS RF Front-End of Low Noise Amplifier for LTE System Applications Integrating FPGAs†Asian Journal of Information Technology, ISSN No: 1682-3915, Vol No.15, Issue No.20, page: 4040-4047, December 2016.

      [28] P Bala Gopal, K Hari Kishore, B.Praveen Kittu “An FPGA Implementation of On Chip UART Testing with BIST Techniquesâ€, International Journal of Applied Engineering Research, ISSN 0973-4562, Volume 10, Number 14 , pp. 34047-34051, August 2015

      [29] S Nazeer Hussain, K Hari Kishore "Computational Optimization of Placement and Routing using Genetic Algorithm†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.47, page: 1-4, December 2016.

      [30] N Bala Gopal, K Hari Kishore "Analysis of Low Power Low Kickback Noise in Dynamic Comparators in Pacemakers†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.44, page: 1-4, November 2016.

      [31] S Nazeer Hussain, K Hari Kishore "Computational Optimization of Placement and Routing using Genetic Algorithm†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.47, page: 1-4, December 2016.

      [32] N.Prathima, K.Hari Kishore, “Design of a Low Power and High Performance Digital Multiplier Using a Novel 8T Adderâ€, International Journal of Engineering Research and Applications, ISSN: 2248-9622, Vol. 3, Issue.1, Jan-Feb., 2013.

      [33] Harikishore Kakarla, Madhavi Latha M and Habibulla Khan, “Transition Optimization in Fault Free Memory Application Using Bus-Align Modeâ€, European Journal of Scientific Research, Vol.112, No.2, pp.237-245, ISSN: 1450-216x135/1450-202x, October 2013.

      [34] T.Padmapriya, Ms. N. Dhivya, Ms U. Udhayamathi, “Minimizing Communication Cost In Wireless Sensor Networks To Avoid Packet Retransmissionâ€, International Innovative Research Journal of Engineering and Technology, Vol. 2, Special Issue, pp. 38-42.

      [35] S.V.Manikanthan and K.Baskaran “Low Cost VLSI Design Implementation of Sorting Network for ACSFD in Wireless Sensor Networkâ€, CiiT International Journal of Programmable Device Circuits and Systems,Print: ISSN 0974 – 973X & Online: ISSN 0974 – 9624, Issue : November 2011, PDCS112011008.

      [36] M. Rajesh, Manikanthan, “GET-UP-AND-GO EFFICIENT MEMETIC ALGORITHM BASED AMALGAM ROUTING PROTOCOLâ€, International Journal of Pure and Applied Mathematics, ISSN NO:1314-3395, Vol-116, No. 21, Oct 2017.

      [37] Rajesh, M., and J. M. Gnanasekar. "An optimized congestion control and error management system for OCCEM." International Journal of Advanced Research in IT and Engineering 4.4 (2015): 1-10.

  • Downloads

  • How to Cite

    Bindu Swetha, P., Kishore Sonti, V., & Murali, A. (2017). VLSI design for efficient RSD-Based ECC processor using Karatsuba algorithm. International Journal of Engineering & Technology, 7(1.5), 164-169. https://doi.org/10.14419/ijet.v7i1.5.9140