VLSI design for efficient RSD-Based ECC processor using Karatsuba algorithm

  • Authors

    • Pasluri Bindu Swetha
    • V.J. Kishore Sonti
    • A. Murali
    2017-12-31
    https://doi.org/10.14419/ijet.v7i1.5.9140
  • Application Specific Instruction-set Processor (ASIP), Elliptic Curve Cryptography (ECC), Field Programmable Gate Array (FPGA), Karatsuba–Ofman Multiplication, Redundant Signed Digit (RSD).

  • Abstract

    In this paper, an exportable application-particular direction set elliptic bend cryptography processor in view of repetitive marked digit portrayal is proposed. The processor utilizes broad pipelining strategies for Karatsuba– Of man strategy to accomplish high throughput augmentation. Moreover, an effective particular viper without correlation and a high throughput measured divider, which brings about a short data path for expanded recurrence, are actualized. The proposed design of this paper investigation the rationale size, region and power utilization utilizing Xilinx 13.2. The expansion for the task is Vedic Sutra – Nikhilam Sutra.

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  • How to Cite

    Bindu Swetha, P., Kishore Sonti, V., & Murali, A. (2017). VLSI design for efficient RSD-Based ECC processor using Karatsuba algorithm. International Journal of Engineering & Technology, 7(1.5), 164-169. https://doi.org/10.14419/ijet.v7i1.5.9140

    Received date: 2018-01-11

    Accepted date: 2018-01-11

    Published date: 2017-12-31