Design and FPGA Implementation of Digital Down Converter for LTE-SDR Receiver
-
2018-03-23 https://doi.org/10.14419/ijet.v7i2.9242 -
Digital Down Converter, FIR, FPGA, Long Term Evolution(LTE), LPF, NCO, SDR, SystemVue, UMTS, VSA. -
Abstract
Due to huge demand for high data rate transmission, there is requirement for efficient design of Digital Down Converter (DDC) in wireless communications. DDC is an indispensable part in modern communication, as for higher frequencies it is difficult to down convert the frequency directly to the baseband frequency. Hence a super heterodyne receiver is used to convert the received signal into an intermediate frequency and the intermediate frequency is then converted into the baseband frequency. The architecture of DDC mainly consists of two parts; first one is demodulation and second one is decimation system. The first stage performs the demodulation and the second stage decimation system performs the operation of filtering and decimation. This paper discusses the design and FPGA implementation of DDC for the LTE-SDR receiver for band5 in LTE(UMTS) standards. The design and FPGA implementation of DDC for LTE-SDR is developed and tested using SystemVue software and Xilinx ML507 FPGA board. The results show that simulation results and FPGA implementation results are very close to each other, so the designed DDC can be used in real time LTE SDR application with hardware as FPGA for efficient processing of data with minimum number of resources and at higher operating frequency.
-
References
[1] Rashmi M Mani and Abdul Imran Rasheed, “Design and Implementation of WDF for Digital Down Converter on FPGA for LTE Application,†International Conference on Advances in Electronics, Computers and communications (ICAECC), 2014.
[2] Emil Krantz, “Design of a Digital Down Converter for LTE in an FPGAâ€, Bachelor’s Thesis in Electronics, University of GAVLE, June 2010.
[3] Chandrasekhar K, Farooq Ulla Khan and Shobha C.R, “Design of Digital Up-Down Converter for LTE-RRH in Digital Radio System,†International Journal of Electronics Communication and Computer Engineering, vol. 4, 2013.
[4] Proakis J.G and Manolakis D.G, “Digital Signal Processing, Principles, Algorithms and Applicationsâ€, Fourth Edition, Pearson Education Ltd, 2007.
[5] Understanding CIC Compensation Filters, Altera Corporation, 2007.
[6] Sanjit K. Mitra, “Digital Signal Processing A Computer-Based Approachâ€, Second Edition, Tata McGraw-Hill Publishing Company Limited, 2001.
[7] Zhang Yuan, Yuan Xingmeng and Qin Jian, “Research and Implementation of the Digital Intermediate Frequency in LTE Superheterodyne Transmitterâ€, 8th IEEE International Conference on Communication Software and Networks, 2016.https://doi.org/10.1109/ICCSN.2016.7586666.
[8] 3GPP TS 36.101 V9.4.0, (2010-06). User Equipment (UE) radio transmission and reception (Release 9).
[9] M. Lohning, T. Hentschel and G. Fettweis, “Digital down conversion in software radio terminalsâ€, Proc. of the 10thEuropean Signal Processing, pp. 1517-1520, Sept. 2000.
[10] T. Hentschel and G. Fettweis, “Sample rate conversion for software radioâ€, IEEE Communications Magazine, pp: 142-150, Aug. 2000.https://doi.org/10.1109/35.860866.
[11] Song Wenmiao, “Designing modified digital down conversion using modern digital signal processingâ€, 2nd International Conference on Consumer Electronics, Communications and Networks, 2012.
[12] Song Wenmiao, “Implementation of digital IF receiver based on SDR using DSP builderâ€, Proceedings of IEEE International Conference of MAPE2011; Date: 1-3 November 2011.
[13] G. Stephen and R. W. Stewart, “High-speed sharpening of decimating CIC filterâ€, Electronics Letters Issue Date: 14 Oct.2004 Volume: 40 Issue: 21 On page(s): 1383-1384 25 October, 2004.
[14] R. H. Walden, “Analog-to-digital converter survey and analysisâ€, Selected Areas in Communications, IEEE Journal on, vol. 17, no. 4, pp. 539-550, 1999.https://doi.org/10.1109/49.761034.
[15] T. Hentschel, M. Henker and G. Fettweis, “The digital front-end of software radio terminalsâ€, Personal Communications, IEEE, vol. 6, no. 4, pp. 40-46, 1999.https://doi.org/10.1109/98.788214.
-
Downloads
-
How to Cite
Telagathoti, P., Aparna, M., & Sridevi, P. V. (2018). Design and FPGA Implementation of Digital Down Converter for LTE-SDR Receiver. International Journal of Engineering & Technology, 7(2), 421-426. https://doi.org/10.14419/ijet.v7i2.9242Received date: 2018-01-22
Accepted date: 2018-02-26
Published date: 2018-03-23