A 2.4 GHz low noise amplifier design at 130nm CMOS technology using common gate topology for WiFi / WiMAX application

  • Authors

    • M. Ramana Reddy
    • N.S Murthy Sharma
    • P. Chandra Sekhar
    2017-12-31
    https://doi.org/10.14419/ijet.v7i1.3.9270
  • CG LNA, CMOS, TSMC.

  • Abstract

    The proposed work shows an innovative designing in TSMC 130nm CMOS technology. A 2.4 GHz common gate topology low noise amplifier (LNA) using an active inductor to attain the low power consumption and to get the small chip size in layout design. By using this Common gate topology achieves the noise figure of 4dB, Forward gain (S21) parameter of 14.7dB, and the small chip size of 0.26 mm, while 0.8mW power consuming from a 1.1V in 130nm CMOS gives the better noise figure and improved the overall performance.

  • References

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  • How to Cite

    Ramana Reddy, M., Murthy Sharma, N., & Chandra Sekhar, P. (2017). A 2.4 GHz low noise amplifier design at 130nm CMOS technology using common gate topology for WiFi / WiMAX application. International Journal of Engineering & Technology, 7(1.3), 69-73. https://doi.org/10.14419/ijet.v7i1.3.9270

    Received date: 2018-01-24

    Accepted date: 2018-01-24

    Published date: 2017-12-31