Improved Gardner Symbol Timing Recovery based on Digital Control Theory


  • Saadi A. Alobaidi



Gardner algorithms, Symbol Timing Recovery, Digital Control Theory.


The study and investigation of Gardener timing error detection performance over Quadrature phase shift keying (QPSK) modulator based on digital control theory is presented in this paper. The stability demonstration of the following performance in any design by open loop techniques and normalizing timing error detection has been examined in MATLAB environments. The recovery of time symbol in second order loop transfer functions has capability to track the down phase with frequency offset situations. The performance of modulation scheme was observed to get lower bit error rate (BER). The proposed algorithms introduced a new technique to provide fewer samples per symbol and less complication due to collaboration with Fourier Transform in coherent receiver and elimination of multiplications. The Gardener timing recovery could operate in 2 samples in the symbol arrangements to enable the minimum receiver complexity. The simulation results shows that the inherent time jitter is outperforms the Gardener algorithms for low roll off factors and despite the reduction of complexity compared with existing techniques.


[1] Y. Li, M. Li, Y. Poo, J. Ding, M. Tang, and Y. Lu, “Performance analysis of OOK, BPSK, QPSK modulation schemes in uplink of ground-to-satellite laser communication system under atmospheric fluctuation†,Optic Communication, vol. 317, pp. 57–61, 2014.

[2] H. Sun, K.-T. Wu, "Clock recovery and jitter sources in coherent transmission systems", Proc. OFC/NFOEC, pp. 1-3, 2012

[3] D. Zibar, A. Bianciotto, Z. Wang, A. Napoli, B. Spinnler, "Analysis and dimensioning of fully digital clock recovery for 112 Gb/s coherent polmux QPSK systems", Proc. 35th ECOC, pp. 1-2, 2009-Sep.

[4] F. M. Gardner, “Interpolation in Digital Modems – Part I: Fundamentals †, IEEE Trans. Comm., COM-41, pp. 501-507, Mar. 1993.

[5] L. Barletta, R. Disarò, M. Magarini, A. Spalvieri, "Post-filter optimization in timing recovery based on square-law detection", IEEE Photon. Technol. Lett., vol. 25, pp. 821-824, May 2013.

[6] M. Oerder, H. Meyr, "Digital filter and square timing recovery", IEEE Trans. Commun., vol. 36, pp. 605-612, May 1988

[7] S. J. Lee, “A new non-data-aided feedforward symbol timing estimator using two samples per symbolâ€, IEEE Commun. Lett., vol. 6, pp. 205-207, May 2002.

[8] M., Yan, et al., “Rasmussen, J.C. Digital clock recovery algorithm for nyquist signalâ€, Proceedings of the Optical Fiber Communication Conference/National Fiber Optic Engineers Conference 2013, Anaheim, CA, USA, 17–21 March 2013; Optical Society of America: Los Angeles, CA, USA, 2013.

[9] N. Kikuchi, T .Yano, H.R. Riu, “ FPGA prototyping of single-polarization 112-gb/s transceiver for optical multilevel signaling with intensity and delay detectionâ€, J. Lightwave Tech. 2016, 34, 1762–1769

[10] A. Josten, B. Baeuerle, M. Song, E. Pincemin, D. Hillerkuss,; J. Leuthold, “Modified Godard algorithm applied on a fractional oversampled signal to correct cd, polarization, and cfoâ€, In Proceedings of the Signal Processing in Photonic Communications, Vancouver, BC, Canada, 18–20 July 2016; Optical Society of America: Boston, MA, USA, 2016.

[11] H. Sun, K. Wu, “A novel dispersion and pmd tolerant clock phase detector for coherent transmission systems. In Proceedings of the Optical Fiber Communication Conference and Exposition (OFC/NFOEC), Los Angeles, CA, USA, 6–10 March 2011.

[12] A. Josten, B. Baeuerle, E. Dornbierer, J. Boesser, F. Abrecht, D. Hillerkuss, J. Leuthold, “ Multiplier-Free Real-Time Timing Recovery Algorithm in the Frequency Domain Based on Modified Godardâ€, In Proceedings of the Signal Processing in Photonic Communications, Boston, MA, USA, 27 June–1 July 2015; Optical Society of America: Boston, MA, USA, 2015

[13] L. Huang, D. Wang, A.P.T. Lau, C. Lu, S. He, "Performance analysis of blind timing phase estimators for digital coherent receivers", Opt. Express 2014, 22, 6749–6763, 2014

[14] N. Kikuchi, T. Yano, H.R. Riu, “FPGA prototyping of single-polarization 112-gb/s transceiver for opticalmultilevel signaling with intensity and delay detectionâ€, J. Lightwave Tech. 2016, 34, 1762–1769, 2016

[15] P. Rapaka, V. Babu, and G. J. Chitra, “ FPGA Implementation of A BPSK Modem†, International Journal of Engineering Research and Application, vol. 3, no. 6, pp. 1976–1985, Dec. 2013

[16] M. Xiao and T. Cheng, “Improved Implementation of Costas Loop for DQPSK Receivers Using FPGAâ€, International Journal of Modern Engineering Research, Vol. 3, pp. 1748-1755, May-June 2013.

[17] N. C. Shivaramaiah, A. G. Dempster, and C. Rizos, “Time-multiplexed offsetcarrier QPSK for GNSSâ€, IEEE Transaction on Aerospace and Electronic Systems, vol. 49, no. 2, pp. 1119–1138, Apr. 2013

[18] F. M. Gardner, “A BPSK/QPSK Timing-Error Detector for Sampled Receivers†, IEEE Transactions on Communication, vol. 34, no. 5, pp. 423–429, May 1986

[19] W. Xin, “Optimization of FPGA Design and Implementation of Timing Recovery in DVB-S2â€, International Conference on Communication, Circuits and Systems. pp. 1265–1269, 2008.

View Full Article: