Reconfigurable on-chip communication link for efficient communication

  • Authors

    • Beulah Hemalatha S BIHER, Chennai
    • Vigneswaran T VIT, Chennai campus, India
    2018-03-23
    https://doi.org/10.14419/ijet.v7i2.9760
  • Genetic Algorithm, On-Chip Communication Link, Optimization, Reconfiguration, System on Chip (SoC).

  • Abstract

    Application specific reconfiguration of On-chip communication link is a fast growing research area in system on chip (SoC) based system design. Optimization of the communication link is important to achieve a trade-off between efficient communication and low power consumption. So achieving both efficient communication and low power consumption requires a special optimization mechanism. Such Optimization problems can be solved using a genetic algorithm. Here, in this paper genetic algorithm based On-chip communication link reconfiguration is presented. The algorithm will optimize efficiency of communication link with constrain of low power consumption. The parameters involved in power consumption and efficient communication link are coded in the chromosomes. By evolutionary iteration the optimal parameters of the communication link are derived that is used for the communication link successfully in the simulated system. The performance of the simulated system is analyzed which shows the out performance of the proposed system.

  • References

    1. [1] Frank Wang, ZhibiaoZhang, (2014), “An adaptive genetic algorithm for mesh-based NoC application mappingâ€, Indonesian journal of Electrical Engineering and Computer science, 12(11), 7869-7875.

      [2] N.Ramalakshmi and N.Hemalatha (2015) “Designing genetic algorithm for network-on-chip architecture†International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE), 12(4), 91-96.

      [3] L. Benini and G. De Micheli, (2002), “Networks on chips: a new SoC paradigmâ€, IEEE Computer, 35(1), 70–78. https://doi.org/10.1109/2.976921.

      [4] GE Fen and WU Ning, (2010) “Genetic algorithm based mapping and routing approach for network on chip architecturesâ€, Chinese Journal of Electronics, 19(1), 91–96.

      [5] A.W. Topol, et al., (2006), “Three-dimensional integrated circuitsâ€, IBM J. Research and Development, 50(4/5), 491-506. https://doi.org/10.1147/rd.504.0491.

      [6] B. S. Feero and P. P. Pande, (2009), “Networks-on-chip in a three dimensional environment: a performance evaluationâ€, IEEE Transactions on Computers, 58(1), 32–45. https://doi.org/10.1109/TC.2008.142.

      [7] RaduMarculescu, UmitY.Ogras, Li-ShiuanPeh, et al., (2009), “Outstanding reasearch problems in NoC design: system, microarchitecture, and circuit perspectivesâ€, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(1), 3–21. https://doi.org/10.1109/TCAD.2008.2010691.

      [8] A.Benymina and P.Boulet, (2007), Multi-objective mapping for NoC architectures, Journal of Digital Information Management (JDIM), 5(6), 378-384.

      [9] T.Bjerregaard and S.Mahadevan, (2006), “Survey of research and practices of network-on-chip, ACM ComputSurv. 38(1), 1-51. https://doi.org/10.1145/1132952.1132953.

      [10] L.Benini, D.Bertozzi, A.Guerri and M.Milano, (2006), “Allocation, scheduling and voltage scaling on energy aware MPSoCsâ€, CPAIOR, 44-58.

      [11] G.Ascia, V.Catania and M.Palesi, (2006), “A Multi-objective Genetic Approach to Mapping Problem on Networkon-Chipâ€, Journal of Universal Computer Science, 2, 370-394.

      [12] D.Shin, J.Kim, (2004), “Power-Aware Communication Optimisation for Networks-on-Chips with Voltage Scalable Linksâ€, in Proc. CODES, 04, 170-175.

      [13] Suleyman Tosun, Ozcan Ozturk, Erencan Ozkan, Meltem Ozen, (2015), “Application mapping algorithms for mesh-based network-on-chip architecturesâ€, The Journal of Supercomputing, 71(3), 995-1017. https://doi.org/10.1007/s11227-014-1348-x.

      [14] Yonghee Yun; Young Hwan Kim, (2016), “Design-time energy optimization for asymmetric multiprocessor system-on-chipâ€, International SoC Design Conference (ISOCC).

  • Downloads

  • How to Cite

    S, B. H., & T, V. (2018). Reconfigurable on-chip communication link for efficient communication. International Journal of Engineering & Technology, 7(2), 417-420. https://doi.org/10.14419/ijet.v7i2.9760

    Received date: 2018-02-27

    Accepted date: 2018-03-07

    Published date: 2018-03-23