Sasipriya, P. and S Kanchana Bhaaskaran, V. 2018. Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL). International Journal of Engineering & Technology. 7, 3 (Jul. 2018), 1548–1551. DOI:https://doi.org/10.14419/ijet.v7i3.14632.