RAGAVENDRAN, U; RAMACHANDRAN, M; ., . Low Power and Low Area Junction-less Tunnel FET Design. International Journal of Engineering & Technology, [S. l.], v. 7, n. 3.1, p. 155–157, 2018. DOI: 10.14419/ijet.v7i3.1.17076. Disponível em: https://sciencepubco.com/index.php/ijet/article/view/17076.. Acesso em: 4 may. 2024.