U. Saravanakumar, P. Suresh, and S. Vimal, “Low-power, low-latency transceiver design using d-TGMS flip-flop for on-chip interconnects”, IJET, vol. 7, no. 1, pp. 106–109, Jan. 2018, doi: 10.14419/ijet.v7i1.8730.